Dolphin Integration launch an innovative IP portfolio for 28 nm multimedia SoC
Grenoble, France – August 1, 2014 -- As the time is ripe, Dolphin Integration announce their 28 nm offering at TSMC HPM, with a broad range of products to address the pending challenges of multimedia SoC. Based on 30 years of design experience, Dolphin Integration reveal their intent to support leading Fabless companies to reach their stringent objectives of very low power consumption, small silicon area and low Bill-of-Material.
Critical virtual components have been developed to address two principal markets:
1- Ultra Low-Power applications (Mobile multimedia)
Products | Main characteristics |
Standard-cell library | Reach up to 40 % gain in power consumption thanks to ultra low power design (L = 50 nm) compared to alternative 7-track library |
| |
Reduced Power Kit Library Library of optimized regulators |
|
Islet Construction Kit with its unique Transition Ramp Cell to prevent IR Drop issues and divide the power consumption by more than 2! | |
Memories spRAM ORION | Single Port RAM optimized for ultra low power consumption |
2- Cost-sensitive applications (Home multimedia)
Products | Main characteristics |
Standard-cell library | 5 to 15 % denser after P&R than standard 7-track library (L = 30 nm) |
Audio converter |
|
Reduced Power Kit Library Library of optimized regulators |
|
Memories | Large range of ultra High density memories to reach up to 15% gain in density |
For further information, feel free to email contact@dolphin-ip.com.
For more information about Dolphin Integration's product portfolio, please visit their catalog.
About Dolphin Integration
Dolphin Integration contribute to "enabling mixed signal Systems-on-Chip". Their focus is to supply worldwide customers with fault-free, high-yield and reliable kits of CMOS Virtual Components of Silicon IP, based on innovative libraries of standard cells, flexible registers and low-power memories. They provide high-resolution converters for audio and measurement, regulators for efficient power supply networks, application optimized micro-controllers.
They put emphasis on resilience to noise and drastic reductions of power-consumption at system level, thanks to their own EDA solutions missing on the market for Application Hardware Modeling as well as early Power and Noise assessment In addition strong experiences in ASIC/SoC design and fabrication, plus privileged foundry portal even for small or medium volumes, makes them a genuine one-stop shop covering all customers’ needs for specific requests.
|
Dolphin Design Hot IP
Related News
- INGChips selects Dolphin Integration's Power Management IP Platform for its ultra Low Power Bluetooth Low-Energy SoC in 40 nm eFlash
- Dolphin Integration sets up a large range of sponsored IPs at 55 nm to reduce SoC power consumption by up to 70%
- Dolphin Integration announces the availability of the new generation 28 nm SpRAM generator
- Dolphin Integration unveils extremely dense audio CODECs for application processors at 28 nm and 16 nm
- Dolphin Integration unveils the new generation of PWM audio DAC for Set-Top-Boxes at 28 nm and 40 nm
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |