Recore Systems' IP in the first European multi-core space processor
Enschede, September 4, 2014 - To create Europe’s first multi-core DSP payload processor for future space missions, a pivotal player in space systems has licensed Recore Systems’ many-core processor subsystem IP. Recore’s subsystem IP will be at the center of the next-generation European data analysis and data compression chip for space missions, a so-called payload processor.
Over the past decades, the amount of data produced during space missions has increased significantly while the increase in communication bandwidth from a space vessel to earth has not evolved at the same speed. A solution to the lack of communication bandwidth lies in space vessels only sending relevant and compressed data earth, and thus make optimal use of the limited communication bandwidth available. The processors that analyze, filter and compress the data from the scientific instruments in space are called on-board payload processors.
“Experts working at Europe’s pivotal player in space design integrate our many-core subsystem IP with well-known space IP. They will create the first multi-core, radiation-hard European payload processor for space based on our technology,” says Dirk Logie, CEO of Recore Systems. “The end result will be a powerful payload processor for processing the wealth of data collected in future space missions. We expect that one day in the foreseeable future, our technology will help to explore the Universe.”
In the multi-core payload processor, Recore’s many-core subsystem IP will be merged with existing, proven space technologies such as SpaceWire interfaces. Recore’s many-core subsystem IP consists of multiple Xentium DSPs and associated memories, interconnected with a performant Network-on-Chip.
The first European multi-core space processor is expected to result in new applications and business opportunities in the European space market. The next-generation payload processor chip will be available early 2016.
About Recore Systems
Recore Systems is a Dutch fabless semiconductor company which develops reliable and fault-tolerant heterogeneous many-core processor subsystems. Our mission is to make the many-core life easy for both hardware and software developers. We implement our mission in hardware and software by delivering both many-core embedded Real Time Operating Systems and middleware, as well as many-core hardware subsystem IP tailored to our customer’s specific application needs.
Recore Systems is headquartered in Enschede, The Netherlands. To learn more, please visit www.recoresystems.com.
|
Related News
- MIPS processor cores power Ceragon Networks' next generation multi-core packet radio
- Ultra High-Performance MIPS64 Architecture Powers Cavium Networks' New Multi-Core Processors
- Cambridge Consultants becomes the first authorised design centre for picoChip's multi-core digital signal processor (DSP)
- European Processor Initiative partner SiPearl will provide its general purpose processor for Europe's first EuroHPC exascale supercomputer JUPITER
- CAES' Quad-Core LEON4FT Processor Selected for European Next-Generation Star Sensors
Breaking News
- intoPIX Powers Ikegami's New IPX-100 with JPEG XS for Seamless & Low-Latency IP Production
- Tower Semiconductor and Alcyon Photonics Announce Collaboration to Accelerate Integrated Photonics Innovation
- Qualcomm initiates global anti-trust complaint about Arm
- EnSilica Agrees $18m 7 Year Design and Supply ASIC Contract
- SiliconIntervention Announces Availability of Silicon Based Fractal-D Audio Amplifier Evaluation Board
Most Popular
- Qualcomm initiates global anti-trust complaint about Arm
- Siemens acquires Altair to create most complete AI-powered portfolio of industrial software
- Alphawave Semi Reveals Suite of Optoelectronics Silicon Products addressing Hyperscaler Datacenter and AI Interconnect Market
- EnSilica Agrees $18m 7 Year Design and Supply ASIC Contract
- Rapidus Announces Strategic Partnership with Quest Global to Enable Advanced 2nm Solutions for the AI Chip Era
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |