7 µW always on Audio feature extraction with filter banks on TSMC 22nm uLL
TVS to champion Requirements Driven Verification and Test at DVCon Europe
Bristol, UK, 29 September 2014 – TVS, a leader in software test and hardware verification solutions, today announced that is presenting and exhibiting at the inaugural Design & Verification Conference and Exhibition Europe (DVCon Europe) to be held in Munich on 14-15 October 2014 at the Hilton City hotel. The company will be showcasing its driven verification and analogue mixed-signal (AMS) capabilities, together with other product developments.
DVCon Europe is a new conference for the application of software languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. DVCon has run successfully for over twenty years in Silicon Valley, so event organisers are expecting a great deal of interest in the first DVCon Europe.
AT DVCon Europe, TVS will be presenting two papers and one tutorial:
- TVS’s tutorial: ‘Requirements Driven Verification and Test (RDVT)’ will be on Tuesday October 14th at 11.30-13.00 and will outline what the development standards mandate and how they can be delivered through requirements-driven verification methodology.
- TVS’s first paper: ‘Practical Experience in Automatic Functional Coverage Convergence and Reusable Collection Infrastructure in UVM Verification’ will take place on Wednesday 15 October at 11.30-12 to be presented by TVS’s Suresh Babu in partnership with Roman Wang of AMD.
- TVS’ second paper: ‘Requirements-Driven Verification Methodology (for Standards Compliance)’ will be held later the same day at 16.00-17.00 to be presented by TVS’s Mike Bartley and Serrie Chapman.
On its DVCon Europe booth, Stand 1, TVS will be showcasing its latest capabilities and product developments:
- asureSIGN is a tool for managers, developers and integrators that ensures that product requirements have been successfully tested and implemented.
- asureCOMPLY makes compliance easier with effective verification in the of safety standards compliance.
- AMS VIP (Analogue Mixed-Signal Verification IP), offered as part of TVS’
asureVIP portfolio, is a suite of tools to provide an efficient, re-usable, development strategy that delivers verification, architecture IP, coverage collection and signoff of AMS designs.
Mike Bartley, CEO of TVS and DVCon Chair, stated, “Visitors are invited to check out our tutorial and technical talks or come along to our stand for the latest solution demos and announcements; including asureSIGN, our leading-edge leading Requirements Driven Verification tool and our analogue mixed-signal capabilities - or simply stop by for a chat.”
If you’d like to prearrange a meeting at the event please email Mike Bartley of TVS at: mike@testandverification.com
About TVS
TVS (Test and Verification Solutions Ltd) provides services and products to organisations developing complex products in the microelectronics and embedded systems industries. Such organisations use TVS to verify their hardware and software products, employ industry best practice and manage peaks in development and testing programmes. TVS’ embedded software testing services includes onsite/offshore testing support including assistance with safety certification and security testing. TVS hardware verification services include onsite/offshore verification support and training in advanced verification methodologies. TVS also offers Verification IPs and its own Verification (EDA) signoff tool.
|
Related News
- Aldec to Highlight ASIC Pre-Silicon Verification Spectrum with Network-On-Chip (NoC) Demonstration at DVCon Europe
- Test and Verification Solutions expands its operations in Silicon Valley, USA
- TVS to showcase advanced verification solutions at DVCon USA 2015
- TVS adds web interface to its asureSIGN verification tool for real-time requirements management sign-off status
- Test and Verification Solutions Limited (TVS) Announces Opening of France Office
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |