Cadence Speeds Communication Systems Design Chains
RapidIO Design Kits Based on Motorola IP Work to Bridge Standards and Implementation Gap
San Jose, Calif., July 15, 2002: Cadence Design Systems, Inc. (NYSE: CDN), the world's leading supplier of electronic design products and services, today announced a verification design kit that enables systems integrators to design and verify their communications systems faster by implementing the RapidIO standard for high-speed interconnect. This kit includes Cadence EDA technology, services to apply the technology to specific customer needs, and integration with proven intellectual property (IP) from Motorola, Inc.
Today's move is part of the Cadence Design Chain Initiative, which helps companies tighten development relationships throughout their design chain, optimizing the chain. Incorporating verification information related to Motorola's IP into Cadence standard verification offerings enables joint customers to design-in Motorola's IP more quickly and effectively. Cadence is the first EDA company to license Motorola's RapidIO endpoint technology, and the first to become a sponsoring member of the RapidIO Trade Association.
The RapidIO interconnect architecture addresses the need for reliability, increased bandwidth, and IP reuse for the rapid assembly of communication systems. This packet-switched, high-performance interconnect technology is designed to be compatible with most integrated communications processors, host processors, and networking digital signal processors. According to the RapidIO Trade Association, the standard enables chip-to-chip and board-to-board communications at speeds of ten Gigabits per second and beyond, while maintaining embedded software compatibility with older PCI-based systems at a fraction of the previous pin count.
According to Sam Fuller, president of the RapidIO Trade Association, "The Trade Association was formed by Motorola, Ericsson and other companies to solve the communication industry's burgeoning need for reliability, increased bandwidth, and faster bus speeds in an intra-system interconnect. The collaboration between Motorola and Cadence provides important enabling technology for members and for the open design community."
"As a founding member of the RapidIO Trade Association, Motorola's active participation has lead the way in architectural and IP contributions," said Raj Handa, director of PowerQUICC business development and technical marketing for Motorola's Networking and Communications Systems Division. "Our RapidIO endpoint technology, along with the collaboration with Cadence, will place the RapidIO standard firmly in the design tool flow - enabling Trade Association members and other users of this technology to speed time between standards development and design implementation."
"Today's announcement furthers the Cadence commitment to foster the development and exchange of IP in design chains through the support of open standards," said Rahul Razdan, corporate vice president and general manager of the Cadence Systems and Functional Verification Group. "We have served our communication systems customers with IP-enabled solutions, such as the Cadence Signal Processing Worksystem (SPW), for 10 years. This agreement with Motorola extends our expertise throughout the verification flow, enabling mutual customers to integrate communication systems more efficiently."
Pricing and Availability
Cadence will provide Motorola's parallel RapidIO endpoint IP in a binary form. Customers will need to obtain a license from Motorola to manufacture systems containing this IP. Cadence plans to deliver the RapidIO design kit with existing Cadence tool configurations at no additional charge, beginning in September 2002.
About Cadence
Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. IEEE, the world's largest technical professional society, honored Cadence with its 2002 Corporate Innovation Recognition award. With approximately 5,600 employees and 2001 revenues of approximately $1.4 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services are available at www.cadence.com .
|
Cadence Hot IP
Related News
- Imagination Optimizes PPA and Speeds the Delivery of Low-Power GPUs Using AI-Driven Cadence Cerebrus in the OnCloud Platform
- X-FAB Adopts Cadence EMX Solver's Electromagnetic Simulation Technology to Support Innovative RF Designs Targeted at Communication and Automotive Markets
- M31 Speeds Delivery of Silicon IP by 5X Using the Cadence Library Characterization Solution in the Cloud
- Cadence Innovus Implementation System Speeds Development of New Realtek DTV SoC Solution
- Alango Voice Communication and Voice Enhancement Packages Now Available for Cadence Tensilica HiFi DSP
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |