Credo Tapes Out Industry-leading Serdes IP on 16-nm FinFET+ Process
Completes Port of 28G and 56G SerDes IP
HONG KONG, CHINA and MILPITAS, CA-- November 19, 2014 -- Credo Semiconductor, a global innovation leader in Serializer-Deserializer (SerDes) technology, today announced it has successfully taped out its popular 28G and 56G SerDes transceiver IP on TSMC's 16-nm FinFET+ (FF+) process. By successfully porting its IP to this advanced processing node, Credo enables ASSP, ASIC and SoC designers to deliver solutions that address the growing performance and bandwidth demands of next-generation 100G and 400G networks.
"We have achieved unprecedented performance levels with our silicon-proven SerDes architectures, and expect to continue this trend on 16-nm FF+," said Bill Brennan, CEO of Credo Semiconductor. "Our architecture has broken new ground in the areas of power, noise immunity and jitter performance, and has also enabled us to deliver a 56G SerDes solution using NRZ technology -- a first for the industry. These metrics are not just a testament to the robustness of our technology, but are actually enabling greater innovation in the design of next-generation networking products."
"Porting complex SerDes technology to 16-nmFF+ is no small feat, and the fact that Credo was able to do this so quickly is a significant milestone for the industry," said Richard Wawrzyniak, senior market analyst for ASIC and SoC, Semico Research. "Today's ASSPs, ASICs and SoCs often require very high-performance communications channels, and SerDes is the perfect vehicle to achieve this performance. Credo has provided the right solution to the industry at the right time."
About the Credo SerDes Architecture
Credo employs a SerDes architecture that is designed for industry-leading throughput, power and performance. The Credo SerDes IP boasts unique Rx auto-adaptation which eliminates the need for post-silicon tuning and/or firmware updates and release management, excellent supply noise rejection, and a wide range of Rx input common mode tolerance -- all of which simplify system-level , board-level, and chip-level integration.
Credo expects to make its 28G and 56G SerDes IP on 16nm FF+ available in March of 2015. Companies interested in learning more about the company's current silicon and intellectual property engagement options, as well as future developments should contact Sales@credosemi.com.
About Credo Semiconductor
Credo Semiconductor is a provider of high performance mixed-signal integrated circuits and IP targeting the data center and enterprise networking markets. The company's SerDes technologies enable optimized solutions for leading edge speed, power, and signal processing requirements. For more information: www.credosemi.com
|
Credo Semiconductor Hot IP
Related News
- Credo 16-nm 28G and 56G PAM-4 SerDes Now Available on TSMC FinFET Compact Process
- GUC and Credo Collaborate to Enable 16-nm FinFET+ Chip Development
- GLOBALFOUNDRIES Demonstrates Industry-Leading 56Gbps Long-Reach SerDes on Advanced 14nm FinFET Process Technology
- Synopsys Tools Achieve TSMC Certification for 16-nm FinFET+ Process and Entered 10-nm FinFET Collaboration
- Rambus Tapes Out 112G XSR SerDes PHY on Leading-edge 7nm Process
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |