Valydate Announces Powerful Design Analysis and Verification Technology

Ottawa, Ontario, CANADA -- January 26, 2015 -- Valydate Inc., the leader in Schematic, Signal and Power Integrity analysis, today announced the launch of ValydateVERA™ (VERA), a powerful new schematic reviewer which will allow Valydate’s customers to gain in-depth verification with time/cost savings and the capability to significantly streamline their design cycles. As schematics become increasingly complex, proper test and review techniques become even more important. VERA systematically improves the business performance of electronic design teams to gain competitive and faster-to-market advantages.

Powered by Valydate’s patented verification engine, VERA is an invaluable complement to the design process which saves design teams hundreds of hours of visual inspection and lab debug time by automating 100+ proprietary checks for each net within a schematic. VERA fully inspects schematics using pre-defined checks and an extensive intelligent model component library.

Key Features of Vera

Interoperability with all major schematic capture tools
100+ built-in checks
Full inspection of 100% of nets in a schematic
Easy setup and intuitive operation
Multi-board interconnect analysis
Ability to create custom device models
Intelligent results post-processing
Extensive intelligent model library included

Proven using hundreds of client designs over the last five years, VERA enables reduced hardware cycles which lead to faster time-to-market; reduction in development; testing and warranty costs; faster integration to high yield manufacturing; improved yield and decreased field returns; and superior product quality.

“VERA has the capability to integrate seamlessly into industry-leading schematic capture tools where clients benefit from the elimination of design errors early in hardware design cycles, when these errors have the least impact on time, quality and cost,” said Michael Alam, CEO of Valydate. “Now a critical complement to the design process, VERA is the most cost effective method to fully review schematic design.”

Valydate will be demonstrating this week at DesignCon 2015, from January 27 to 29, in Santa Clara. Attendees are encouraged to drop by the Valydate Booth #953 for a first hand demonstration.

About ValydateVERA™
Launched in 2014, ValydateVERA™ is a powerful design analysis and verification tool that saves design teams hundreds of hours of visual inspection and lab debug time by automating 100+ proprietary checks for each net within a schematic. Fully inspecting schematics using pre-defined checks and an extensive intelligent model component library, VERA is the most cost effective method to fully review schematic design.

VERA is available now for purchase or licensing opportunities. For more information on VERA and pricing or licensing, please visit http://vera.valydate.com/

About Valydate
Valydate Inc. is a leading Schematic, Signal and Power Integrity analysis company that offers an innovative and automated approach to schematic review and validation. The Company’s patented verification engine provides automated inspection and review beyond human ability. As schematics become increasingly complex, proper test and review techniques become even more important. Proven through use in hundreds of designs over 5 years, clients benefit from the elimination of design errors early in the hardware design cycle, when they have the least impact on time, quality and cost. Valydate’s clients include those in the telecom, defense and aerospace, and photonics sectors.

Founded in 2010, Valydate operates worldwide. For more information, visit http://www.valydate.com