Sony Joins FDSOI Club
Junko Yoshida
1/30/2015 05:15 PM EST
MADISON, Wis. — Sony Corp. revealed that the company’s next-generation Global Navigation Satellite System (GNSS) chip will use 28-nm Fully Depleted Silicon On Insulator (FDSOI) process.
The test chip based on the FDSOI process marks a dramatic reduction in power consumption. A Sony engineer, who spoke at the SOI Industry Consortium in Tokyo, told the audience that Sony was able to cut power consumption in its GNSS chip from 10mW to 1mW.
The Japanese company used STMicroelectronics’ 28nm FDSOI design kit, and manufactured its FDSOI samples at ST's fab.
E-mail This Article | Printer-Friendly Page |
Related News
- Sony Senior VP & Playstation LSI Leader, Takayasu Muto Joins Secure-IC's Strategic Committee
- Cortus joins RISC-V fan club
- Synopsys Joins GLOBALFOUNDRIES' FDXcelerator Partner Program to Enable Innovative Designs Using the FD-SOI Process
- Sony To Use FD-SOI in Stacked Image Sensors
- UMC Joins Elite Club
Breaking News
- Baya Systems Raises $36M+ to Propel AI and Chiplet Innovation
- Andes Technology D45-SE Processor Achieves ISO 26262 ASIL-D Certification for Functional Safety
- VeriSilicon and Innobase collaboratively launched second-generation Yunbao series 5G RedCap/4G LTE dual-mode modem IP
- ARM boost in $100bn Stargate data centre project
- MediaTek Adopts AI-Driven Cadence Virtuoso Studio and Spectre Simulation on NVIDIA Accelerated Computing Platform for 2nm Designs
Most Popular
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- Arm Chiplet System Architecture Makes New Strides in Accelerating the Evolution of Silicon
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X