eInfochips announces eMMC 5.0 Verification IP
Supports eMMC 5.0 from JEDEC, for high performance embedded flash memory systems
Ahmedabad -- Feb 5, 2015 -- eInfochips, a leading Product Engineering Services company has announced the availability of the eMMC 5.0 Verification IP (VIP). Companies designing the next generation embedded flash memory systems can improve the reliability and performance of their products using the eInfochips eMMC 5.0 VIP. The eMMC 5.0 will accelerate RTL verification cycles of JEDEC standards compliant devices for mobiles, tablets and other consumer devices. In line with the Verification IP, eInfochips also offers ASIC and FPGA verification services for companies in the storage industry.
The eMMC 5.0 standard from JEDEC (JESD84-B50) will improve data throughput from 1.6 Gbps to 3.2 Gbps (over pervious standards), improving memory access speeds for consumer devices. The architecture encompasses the flash memory and its controller on a single IC package for use as an embedded Non-Volatile Memory System (NVMS).
Previous versions of the eMMC Verification IP developed by eInfochips is a proven environment since 2010-11, deployed by leading global companies. Parag Mehta, the Chief Marketing and Business Development Officer at eInfochips said, “We estimate more than a billion eMMC 5.0 device shipments in 2015-16. Our eMMC 5.0 VIP bundled with verification service will deliver reliable, high-performance memory systems for the market.”
eInfochips eMMC 5.0 VIP
The eMMC 5.0 VIP enables design and verification engineers to extensively test the functionality of embedded memory systems. Verification Models and Compliance Test Suites are developed in SystemVerilog (SV) and support UVM environment. The verification architecture includes key modules like the Host Controller and the eMMC device Controller.
The VIP bundles in deliverables like Sample Use Cases, Sanity Test Cases, Verification Environment (to be integrated) and the User Guide.
The eMMC 5.0 VIP is available now to select customers, companies can write to marketing@einfochips.com for more information. The complete feature set and specifications data sheet can be found here.
eInfochips VIP Development and Verification Practice
eInfochips has developed 32 complex VIPs for top global EDA companies and end-customers. Their experience includes VIPs for the latest high-speed and low-power protocol standards, like MIPI, SERDES, USB 3.0, DDR3, HDMI and eMMC. Today, eInfochips has contributed to VIPs that are deployed by hundreds of customers to bring confidence to their ASIC, SOC and FPGA designs.
About eInfochips
eInfochips is a global product innovation partner recognized for technology leadership by Gartner, Frost & Sullivan, NASSCOM and Zinnov. eInfochips has contributed to 500+ products for top global companies, with more than 10 million deployments across the world.
Visit us at www.einfochips.com
|
Related News
- Mentor Graphics Delivers Veloce Emulation Solutions for the Verification of High-Performance Memory Products
- Avery Design Systems Announces eMMC 5.0 Verification IP Solution
- Achronix Pushes the Boundaries of Networking with 400 GbE and PCIe Gen 5.0 for SmartNICs
- Intel Launches Agilex 7 FPGAs with R-Tile, First FPGA with PCIe 5.0 and CXL Capabilities
- OIF Marks 25th Anniversary, Launches New Physical & Link Layer Working Group Electrical Project and Adds 112G VSR Clause to CEI 5.0 IA at Q1 Technical and MA&E Committees Meeting
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |