English
TVS announces new CPU Verification tool development
February 23, 2015 -- TVS is pleased to announce the development of a new “Event Stream Generator”.
Processors (CPU, GPU, DSP, etc.) are becoming more complex and require more verification. The current best practise in processor verification is instruction stream generation.
The TVS instruction stream generator (asureISG) will have the following major features
- Offline generation: the instructions are generated in advance of simulation for quicker generation speeds.
- Sequence generation: sequences of instructions can push a design into the corners where the bugs lurk!
- Multicore support: asureISG can be programmed to generation instructions for multiple cores allowing it to generate sequences of instruction streams for multiple cores. Those sequences can interlaced with defined synchronisation points for multicore verification.
- Coverage support: coverage models can be built into the generation to help direct the generation.
asureISG is currently under development with TVS key clients but we are open to more early adopter partners who want to influence the development.
|
||||||
Related News
- Imperas and Metrics Collaborate to Jump Start RISC-V Core Design Verification Using Open Source Instruction Stream Generator
- Cadence to Optimize Digital Full Flow and Verification Suite for Arm Cortex-A78 and Cortex-X1 CPU Mobile Device Development
- TVS extends CPU Verification Capability
- TVS adds web interface to its asureSIGN verification tool for real-time requirements management sign-off status
- Xilinx Ships New Release Of System Generator For DSP Development Tool With Full Support For Latest MatLab & Simulink Software
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |