Digital Blocks Announces 2nd Gen Audio/Video & Data Hardware Protocol Stacks Supporting MPEG2 Transport Stream (TS), RTP, and UDP/IP Protocols
GLEN ROCK, New Jersey, March 24, 2015 – Digital Blocks, a leading developer of low-latency, high performance networking IP Cores for Video & Data Networking Applications, today announces 2nd Generation Hardware Protocol Stacks supporting a mix of MPEG2 Transport Stream (TS), RTP, and UDP/IP Protocols for network adapter cards with 10/100/1000 Mbps or 10/40/100 Gbps network links.
The following tables list Digital Blocks Hardware Protocol Stacks IP Cores:
IP Core | Hardware Protocol Stack Support |
DB-UDP-IP | UDP/IP |
DB-RTP-UDP-IP | RTP/UDP/IP |
DB-MPEG-TS-UDP-IP | MPEG-TS/UDP/IP |
DB-MPEG-TS-RTP-UDP-IP | MPEG-TS/RTP/UDP/IP |
Note that all Digital Blocks Hardware Protocol Stacks support Transmit (Encapsulation) & Receive (De-capsulation) as well as Transmit-only or Receive-only configurations.
Price and Availability
Digital Blocks Protocol Hardware Stack IP Cores are available immediately in synthesizable Verilog, along with a simulation test bench with expected results, datasheet, and user manual. For further information, product evaluation, or pricing, please go to Digital Blocks at http://www.digitalblocks.com
About Digital Blocks
Digital Blocks designs silicon-proven IP cores for technology systems companies, reducing customer’s development costs and significantly improving their time-to-volume goals. Digital Blocks is located at 587 Rock Rd, Glen Rock, NJ 07452 (USA). Phone: +1-201-251-1281; eFax: +1-702-552-1905; Media Contact: info@digitalblocks.com; Sales Inquiries: info@digitalblock.com; On the Web at www.digitalblocks.com
|
Digital Blocks Hot IP
Related News
- Digital Blocks Releases 2nd Gen UDP/IP Hardware Stack / UDP/IP Off-Load Engine (UOE) Targeting High-Frequency Trading Systems
- Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with targeted applications in DMA Streaming of Video and Data over PCIe or UDP/IP Network Interface.
- Digital Blocks Announces UDP/IP Hardware Stack / UDP/IP Off-Load Engine (UOE) Targeting High-Frequency Trading Systems
- CAST Expands Popular UDP/IP Networking Cores Line
- Mobiveil Announces Fully Compliant RapidIO 10xN (Gen 3) Digital Controller IP Supporting Multi-Channel DMA, Data Message and Data Streaming at 40Gbps
Breaking News
- HPC customer engages Sondrel for high end chip design
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- TSMC drives A16, 3D process technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
E-mail This Article | Printer-Friendly Page |