Andes CPU Core Wins New Socket in MediaTek SoCs

AndesCore Selection Based on Offering
Smallest Die Area and Lowest Power Consumption Among Competitive Options

HSINCHU, TAIWAN - April 2, 2014 - Andes Technology Corporation, the leader in developing easy to integrate, scalable, and configurable CPUs and platforms, today announced that MediaTek Inc., a leading fabless semiconductor company, has adopted the AndesCore™ N9 CPU IP in their SoCs. The AndesCore™ N9 is intended for deeply embedded applications that require optimal interrupt response time, efficient performance and compact code size, including wireless networking and sensors.

"We are thrilled that AndesCore N9 was selected for use in the MediaTek SoCs," said Dr. Charlie Su, Chief Technical Officer and SVP of R&D at Andes. "The N9 dramatically reduces the instruction memory size and cost of the SoC through higher code density, when compared to legacy 8- or 16-bit MCUs. Despite the N9's compact size, it still provides more than 40 percent better performance than competing 32-bit processor cores to enable functionality such as 802.11 drivers and TCP/IP protocol stack for network applications, GPIO and PWM for intelligent control, as well as UART and SPI interfaces for device communication."

According to market analyst BI (Business Intelligence), smart home device shipments will grow faster than smart phones or other portable devices, at a compound annual rate of 67 percent for the next five years. The market research firm expects as many as 1.8 billion units to ship in 2019, including safety and security devices such as internet-connected sensors, monitors, cameras, and alarm systems and energy management components such as smart thermostats and lights. As Andes customers produce SoCs for this market opportunity, embedded processors such as the N9 will continue to see strong demand.

About the AndesCore™ N9 Family

The AndesCore N9 Family is intended for deeply embedded applications that require optimal interrupt response features, including wireless networking and sensors as in microcontrollers, automotive electronics, and industrial control systems. The low-power N9 Family of processors features low gate count, low interrupt latency, and low-cost debug. The processor family provides superior performance and excellent interrupt handling response while meeting the challenges of low dynamic and static power constraints. The AndesCore N9 Family of CPU cores implement v3, the patented AndeStar™ 32-bit RISC-style CPU architecture. The designer can configure certain parameters to adjust the CPU's size, power, and performance. For example, the N9 core can be configured with 16 or 32 general registers, two or three read ports on the register file, one or two write ports, a fast or a small multiplier, a 24-bit or 32-bit address space, and different bus (APB, AHB, AHB-Lite, or AXI) interfaces to connect to the rest of the system. Its bigger cousin N10 Family supports caches and an optional floating-point coprocessor.
About Andes Technology Corporation

Andes Technology Corporation is a leader in developing high-performance/low-power 32-bit processors and its associated SoC platforms to serve the rapidly growing embedded system applications worldwide. The company's broad and deep technical expertise in microprocessor, system architecture, operating system, software tool chain development, and SoC VLSI implementation enables designers to shorten their time-to-market with quality designs. In addition, Andes' innovative configurable platform solution allows design teams to construct unique system architecture and hardware/software partitioning to achieve the optimal SoC.