Defacto Announces a Unified Design Flow to Ensure Coherency Between RTL, UPF, IPXACT and SDC
Grenoble, France, Sunnyvale, CA – May 6, 2014 – Defacto Technologies, the leading provider of RTL platforms that help achieve early design closure, announced today its unique EDA solution to help build a unified design flow that guarantees coherency between multiple languages and standards: RTL, power intent UPF, IPXACT and SDC. The unified design flow will be demonstrated at the Design Automation Conference (DAC) held in San Francisco starting June 1, 2014.
“We continue to help chip designers build robust, extensible and custom design flows at RTL. Beyond our RTL editing and structural verification solution, we will be unveiling at DAC new EDA breakthrough technologies in different areas such as RTL “low power” exploration, IPXACT and SDC support,” said Chouki Aktouf, Defacto Technologies co-founder and CEO. “Our unified solution helps SoC designers build coherent and highly maintainable front-end design flows where the construction and the verification of complex RTL designs is automatically linked to different views such as UPF, IPXACT and SDC. With the adoption of Defacto’s EDA unified design flows, key semiconductor companies can truly expect a high degree of maintainability for front-end design flows and drastically decrease engineering costs.”
Defacto team will be presenting its solutions at DAC in booth #807. For presentation and demo requests, please contact Defacto at inforeq@defactotech.com.
About Defacto
Defacto Technologies is an innovative chip design software company providing breakthrough RTL platforms to enhance IP integration, design verification and RTL signoff of IP cores and system on chips (SoC). Defacto EDA solutions help solve design problems in areas such as SoC integration, low power, clock verification, RTL signoff, ECO and DFT. Founded in 2003, the company has offices near Grenoble, France, and in Sunnyvale, California, USA, and sales offices in China, Japan, Taiwan, South Korea, Singapore, Israel and Europe. For more information, please visit www.defactotech.com
|
Related News
- Defacto Announces STAR 8.0 and Provides a Unified "All-in-One" SoC Design Solution to Help Conciliating Between RTL, IP-XACT, UPF, SDC, and Physical Design Information
- Magma and ChipX Team to Deliver Unified RTL-to-GDSII Design Flow for Structured ASIC Platforms
- Achronix and Mentor Partner to Provide Link Between High-Level Synthesis and FPGA Technology
- Defacto Technologies Announces Synapse Design in collaboration with a major semiconductor company Reduces Simulation Time by 5X When using Defacto's RTL Design Solutions
- Synopsys and Helic Deliver Unified Electromagnetic-Aware Analog and RF Custom Design Flow
Breaking News
- Alphawave Semi Q4 2024 Trading and Business Update
- ST-GloFo fab plan shelved
- Arm Chiplet System Architecture Makes New Strides in Accelerating the Evolution of Silicon
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X
Most Popular
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- Altera Launches New Partner Program to Accelerate FPGA Solutions Development
- Electronic System Design Industry Posts $5.1 Billion in Revenue in Q3 2024, ESD Alliance Reports
- Breaking Ground in Post-Quantum Cryptography Real World Implementation Security Research
- YorChip announces patent-pending Universal PHY for Open Chiplets
E-mail This Article | Printer-Friendly Page |