English
Avery Design Systems Takes Focus on MIPI CSI and DSI VIP Solutions
TEWKSBURY, Mass. -- June 08, 2015 -- Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of MIPI VIP supporting the DSI-2, CSI-2 v2.0, C-PHY v1.1, and D-PHY v1.2 standards. This expands Avery’s comprehensive MIPI VIP portfolio which already includes UFS, UFSHCI, Unipro, M-PHY, and Soundwire.
CSI and DSI VIP supports
- CSI Transmitter and Receiver and CCI I2C Master/Slave dual mode models
- DSI Transmitter and Receiver dual mode models
- Packet and CCI message classes
- C-PHY and D-PHY multi-lane physical layer options
- Timing and protocol checks
- Functional coverage
- Protocol analyzer trackers
- Compliance testsuite
Models and compliance testsuites are developed 100% in SystemVerilog and UVM.
“The evolution of displays, cameras, audio, sensor, and storage peripherals in next generation portable devices requires a new level of low power, bandwidth, and interoperability that only the latest DSI and CSI and other MIPI standards deliver. Avery is in a position to assist system integrators in a full range of MIPI, LPDDR, SD/eMMC mobile peripheral VIP solutions including models, protocol compliance tests, and IP partner collaboration to deliver comprehensive verification and compliance”, says Chilai Huang, president of Avery Design Systems.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, UFS, MIPI, DDR/LPDDR, HMC, ONFI/Toggle, NVM Express, SCSI Express, SATA Express, eMMC, SD/SDIO, and CAN FD standards. The company is a member of the Mentor Graphics Value Added Partnership (VAP) program and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
|
||||||
Avery Design Systems Hot Verification IP
Related News
- Upgrade Your Display and Camera SOC's with proven MIPI C-D Combo PHY and CSI / DSI Controller IP Cores for both Tx and Rx
- MIPI DSI and CSI Controllers IP Cores, for your High-Resolution Cameras, Display and Consumer Products, is available for immediate licensing
- Avery Design Systems Verification IP Helps Solid State Storage Controller Startup Validate its Designs and Get to Market Faster
- USB 4.0, MIPI DSI/CSI 2.0, Display Port 1.4, HDMI 2.1, DDR5, PCIe5.0, 1G Ethernet IP Cores and many more Wired Interface IP Cores available for immediate licensing
- MIPI CSI 3, DSI 2 Tx & Rx Advanced Controller & PHY IP Cores available in major Fabs & Nodes for SOC Designs for Imaging and Display Applications
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |