Tensilica Xtensa Processor Beats All Other Processor Cores on Four Real-World Processor Benchmark Tests Conducted by EEMBC

Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)

Enhancements Delivered with New Xtensa V Processor Architecture Widen Tensilica's Performance Lead in the Embedded Processor Market

Santa Clara, Calif., August 26, 2002 – Tensilica, Inc., the leading provider of configurable and extensible processors, today announced that the Xtensa V processor core, introduced today, has posted the highest scores ever recorded for a licensable processor core on four key benchmark suites performed by the Embedded Microprocessor Benchmark Consortium (EEMBC): Consumer, Telecom, Office Automation and Networking. The benchmark scores, independently certified by the EEMBC Certification Laboratories (ECL), represent the performance of embedded microprocessors in a variety of real-world applications.  The tests confirmed that that the Xtensa V processor delivers performance that is from 40 percent better to nearly 8.5X that of any other competitor on each of the four tests using a standard "Out-of-the-box" processor configuration. When optimized versions of the Xtensa V processor were tested, the results were up to 33X the closest competitor.

" The EEMBC benchmarks prove that Tensilica's configurable and extensible processor architecture delivers breakthrough features and optimized performance in embedded devices," said Chris Rowen, president and CEO of Tensilica.  "Our new Xtensa V processor not only continues to outperform the competition, but also delivers an architecture that significantly reduces design time and complexity.  As the only configurable and extensible processor supplier to provide comprehensive and automatic software, modeling and EDA support, Tensilica enables the delivery of optimized, customized processors in hours, as opposed to months."

Tensilica's processor generator technology creates a complete, correct-by-construction processor solution – hardware, software environment, modeling and EDA tools – in just over an hour. Each core can be optimized for virtually any application. Changes made by the user to extend the Xtensa processor hardware – adding instructions, registers, processor state and custom execution units - are immediately and automatically reflected in the entire software tool chain, significantly reducing design complexity and time-to-market. By comparison, competitive architectures either prohibit designer-defined extensions or require the designer to manually adjust compilers, assemblers, debuggers, operating systems, instruction set simulators, co-verification models and EDA implementation scripts when user-defined hardware changes are made to the processor RTL.

Details of the Consumermark, Netmark, Telemark and OAmark Scores

EEMBC has developed a suite of benchmark tests that are based on the fundamental algorithms and functions of the most popular embedded processor applications. The Xtensa core posted the best scores of any processor core in both the "Optimized" and "Out of the box" categories on the EEMBC Consumer-mark, Networking-mark, Telecom-mark and Office Automation-mark benchmark suites, outperforming products from several high-profile processor companies.

EEMBC allows two scoring methods: "Out-of-the-box" and "Optimized." "Out-of-the-box" tests measure performance using unmodified C-code, while "Optimized" tests measure performance after modifications, or optimizations, have been made to the C code. The Xtensa core was optimized using the Tensilica Instruction Extension (TIE) language to optimize performance. The TIE language enables designers to develop an unlimited variety of user-defined instructions. No assembly coding was used in the EEMBC benchmarks, and no assembly coding is ever required to utilize the power of TIE extensions.

The EEMBC results show that the base Xtensa processor performs about 43 to 256 percent higher than the ARM1026EJ, the next-fastest processor core, on Out-of-the-box EEMBC benchmarks, while the optimized Xtensa core outperforms the ARM1026EJ by 8X to 33X. In some cases, the Xtensa core outperforms even full-chip, multi-million- transistor standalone processor ICs that are as much as 100 times the size of the Xtensa core, proving the efficiency and integration enabled by the Xtensa architecture and the immense power of designer-defined extensions.

	Clock Speed	Consumer	Networking	Telecom	Office Auto
Processor Cores (Simulated)
Xtensa V "Out of the Box"	260 / 300 / 285 / 360  MHz synthesizable core, 0.13-micron	22.6	9.0	8.7	303.7
ARM-1026EJ-S "Out of the Box"	266 MHz synthesizable core, 0.13-micron	15.8	4.4	3.4	168.8
Xtensa V "Optimized"	260 / 300 / 285 / 360  MHz synthesizable core, 0.13-micron	525.9	37.0	134.9	N/A
ARM 1020E "Out of the Box"	Optimized hard core; 325 MHz in 0.13um	19.3	5.4	4.1	206.2
Processor ICs (Silicon)
NEC VR5000 (MIPS64 ISA) "Out of the Box"	250 MHz	14.5	4.1	3.4	168.9
Texas Instruments TMS320C6203 "Optimized"	300 MHz	N/A	N/A	68.5	N/A

Xtensa V Performance Reflects Significant Enhancements to The Xtensa C/C++ Compiler (XCC)

Compiler performance can have a significant effect on a processor's overall performance. With the release of Xtensa V today, Tensilica has made significant enhancements to its XCC compiler.  The compiler, which was first introduced with the Xtensa IV processor architecture last year, has been optimized to deliver higher performance and reduced code size. New features include cross-file inlining, interprocedural analysis and removal of unused functions, improved alias analysis and register scheduling, and numerous code generation improvements. The result is exceptional performance improvements as evidenced by the EEMBC benchmark scores made public today. 

A comparison between Tensilica's January 2001 EEMBC results and the new results released today illustrate the performance improvements delivered by the Xtensa C/C++ compiler.  Tensilica's Jan. 2001 benchmark scores were produced using the industry-standard GCC compiler.  A comparison of the out-of-the-box EEMBC scores from Jan 2001 to today – which is a comparison of the identical base Xtensa processor hardware but with 2 different compilers – shows that the XCC compiler delivers a stunning 50% improvement in the EEMBC Consumer and Networking benchmarks and a 160% improvement in the Telecom benchmark. The Telecom benchmark benefits from the auto-vectorization capability of XCC for the Vectra DSP engine employed in the Xtensa-configuration used for the EEMBC Telecom suite.

Tensilica has made a number of other improvements to the overall Xtensa processor feature set which are detailed in a separate press release also issued today.

About EEMBC

EEMBC, the Embedded Microprocessor Benchmark Consortium, develops and certifies real-world benchmarks and benchmark scores to help designers select the right embedded processors for their systems. Every processor submitted for EEMBC® benchmarking is tested for parameters representing different workloads and capabilities in communications, networking, consumer, office automation, automotive/industrial, embedded Java, and microcontroller-related applications. With members including leading semiconductor, intellectual property, and compiler companies, EEMBC establishes benchmark standards and provides certified benchmarking results through the EEMBC Certification Labs (ECL) in Texas and California.

About Tensilica

Tensilica was founded in July 1997 to address the fast-growing market for configurable processors and software development tools for high volume, embedded systems. Using the company's proprietary Xtensa Processor Generator, system-on-chip (SOC) designers can develop a processor subsystem hardware design and a complete software development tool environment tailored to their specific requirements in hours. Tensilica's solutions provide a proven, easy-to-use, methodology that enables designers to achieve optimum application performance in minimum design time. The Company has over 140 engineers engaged in research, development, and customer support from its offices in Santa Clara, California; Burlington, Massachusetts; Princeton, NJ; Austin, Texas; Raleigh, NC; Oxford, U.K.; Stockholm, Sweden; Taipei, Taiwan, R.O.C.; and Yokohama, Japan. Tensilica is headquartered in Santa Clara, California (95054) at 3255-6 Scott Boulevard, and can be reached at (408) 986-8000 or via www.tensilica.com on the World Wide Web.
 

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Editor's Notes:

"Tensilica" and "Xtensa" are registered trademarks belonging to Tensilica Inc. EEMBC is a registered trademark of the Embedded Microprocessor Benchmark Consortium.  All other trademarks are the property of their respective holders.

Tensilica's announced licensees are Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, FUJIFILM Microdevices, Fujitsu Ltd., Hughes Network Systems, IC4IC, Ikanos Communications, JNI Corporation, Marvell, Mindspeed Technologies, National Semiconductor, NEC Networks, NEC Solutions, Nippon Telephone and Telegraph (NTT), Olympus Optical Co.Ltd.,  ONEX Communications, Olympus Optical, OptiX Networks, Osaka & Kyoto Universities, TranSwitchCorporation, Trebia Networks, Victor Company of Japan (JVC) and ZiLOG.