Arasan Chip Systems Announces Availability of ONFI 4.0 Compliant NAND Flash Controller IP & PHY Solution
September 3, 2015 -- NAND flash memory applications are ever evolving, placing demands on the designers to continuously push the envelope on performance and power consumption. Arasan addresses these challenges by offering its Arasan ONFI 4.0 Compliant NAND Flash Controller IP solution that provides a performance boost by increasing data transfer rates to 800 MT/s – or 800MB/s for an 8 bit interface – and reduces power consumption by more than 50%.
Focusing on high performance and high reliability, Arasan’s ONFI 4.0 NAND Flash Controller IP solution comprises a high performance digital controller IP core and a hardened Analog PHY which includes ONFI 4.0 compatible I/O pads supporting 1.2v, 1.8v and 3.3v operation. Compliant to the ONFI 4.0 electrical interface, Arasan’s IP core solution, delivered in RTL supports NV-DDR3 up to the specifications full 800 MB/s. The ONFI 4.0 compatible I/O pads support NV-DDR3 operation at 1.2v. These pads differ from typical high speed DDR I/O pads in that they also support 1.8v and 3.3v I/O operation to enable backward compatibility with ONFI 2/3 . The combined Controller IP, analog PHY and the I/O pads shortens time-to-market by reducing SoC designers’ development time otherwise spent on ensuring high speed signal integrity.
Arasan’s ONFI 4.0 NAND controller IP supports SLC, MLC, and TLC NAND Flash up to 1024Gb, synchronous and asynchronous NAND interfaces, page size up to 16KB, BCH ECC engine correcting 32-bit or more errors, and eight chip-selects. Arasan’s ONFI 4.0 NAND Flash Controller IP interfaces to the system’s AXI, AHB or OCP bus. Arasan also provides ONFI 4.0 software stack and drivers. The Silicon Proven ONFI 4.0 NAND PHY IP is available in nodes from 40nm to 16nm for most major foundries.
Arasan will continue to make available its ONFI 2.3 and 3.1 Compliant NAND Flash Controllers along with a Soft NAND PHY with I/O Pads for speeds supporting up to the 3.1 specification.
Availability
Arasan’s ONFI 4.0 NAND Controller Total IP Solution, including Controller IP core in RTL, ONFI 4.0 I/O pads delivered in GDSII, and the optional ONFI 4.0 PHY delivered in GDSII is available now for shipment.
About Arasan
Arasan Chip Systems is a leading provider of Total IP Solutions for mobile and the next generation of Smart applications from home to automobile. Arasan’s high-quality, silicon-proven, Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers, software stacks and drivers, and optional customization services for Ethernet, MIPI, PCIe, USB, UFS, SD, SDIO, eMMC, and UFS. Arasan’s Total IP products serve system architects and chip design teams in applications that require silicon-proven, validated IP, delivered with the ability to integrate and verify both digital, analog and software components in the shortest possible time with the lowest risk.
About ONFI
The Open NAND Flash Interface (ONFI) is an industry Workgroup made up of more than 100 companies that build, design-in, or enable NAND Flash memory. We’re dedicated to simplifying NAND Flash integration into consumer electronic products, computing platforms, and any other application that requires solid state mass storage. We define standardized component-level interface specifications as well as connector and module form factor specifications for NAND Flash.
|
Arasan Chip Systems Hot IP
Related News
- Arasan Announces NAND Flash Controller PHY and I/O Pad IP compliant to ONFI 4.1 Specifications
- Arasan Chip Systems Announces Availability of ONFI 3.2 NAND Flash Controller IP & PHY Solution
- Arasan Chip Systems expands its storage IP Portfolio with ONFI 4.1 PHY and I/O PAD IP seamlessly integrated with its NAND Flash Controller IP for UMC 28nm SoC Designs
- Arasan Chip Systems Announces ONFI 3.0 NV-DDR2 PHY and Patent Pending Dynamically Configurable ECC technology for NAND Flash Controller
- Arasan Announces the Industry's First ONFI v5.0 Compliant NAND Flash IP
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
E-mail This Article | Printer-Friendly Page |