Xilinx and Paxonet Communications Announce Industry's Most Complete Platform FPGA-Based LAN/WAN 10 Gigabit Ethernet Solution
SANTA CLARA, Calif., September 9, 2002 - Xilinx, Inc., (NASDAQ: XLNX) and Paxonet Communications, a Xilinx AllianceCORE™member and leading telecommunications IP and Silicon provider, today announced the immediate availability of Paxonet's 10 Gigabit Physical Coding Sublayer (PCS) and Media Access Controller (MAC) cores for use in Xilinx Virtex-II™ and Virtex-II Pro™ FPGAs. These new AllianceCORE products, together with the 10 Gigabit STS-192 Framer and STS-192 Path Processor cores announced last month, form the industry's first and most complete 10 Gigabit Ethernet LAN and WAN IP core package for programmable systems design. The solution targets applications at the metropolitan edges of the network include multi-service switches, add-drop multiplexers, digital cross connects, traffic aggregators, and test equipment.
"Introducing Paxonet's 10 Gigabit Ethernet IP Cores, combined with its STS-192 IP Cores, positions Paxonet with the industry's most comprehensive range of Ethernet IP Cores, providing our customers with flexible Ethernet LAN and WAN solutions. The multi-gigabit serial I/O capability of Xilinx Virtex-II Pro devices allows customers to take full advantage of these cores and reduces their time to market with an FPGA solution. Because of the lower volumes required in today's telecommunications market, FPGA solutions are frequently more cost effective," said Kevin Wayne Williams, Vice President of Marketing at Paxonet.
"Paxonet's ability to provide a full range of Ethernet and SONET solutions on Xilinx FPGAs enables Metro equipment vendors to implement fully flexible, customizable non-ASIC solutions," said Robert Bielby, senior director of Strategic Solution at Xilinx.
The new 10 Gigabit Ethernet IP Cores are compliant with IEEE P802_3ae Draft 2.1 Physical Coding Sub-Layer specifications and IEEE 802.3 task force draft 5.0 frame specifications. The PCS Core implements a 64- to 66- bit gear box, provides a generic 16-bit microprocessor interface, a variety of performance monitoring counters, and programmable value of control codes and corresponding 7-bit code mappings. The MAC core supports full duplex operation, PAUSE frame based full duplex flow control, both LAN and OC-192c data-rate WAN PHYs, WAN PHY using open loop (IPG stretching) rate control, Link Fault Signaling (LFS), and VLAN tag frames.
Availability The 10 Gigabit Ethernet cores are available immediately from Paxonet Communications. For more information on the Paxonet and Xilinx Ethernet solutions, visit the Xilinx website at www.xilinx.com/ipcenter or www.paxonet.com. These products can be licensed from Paxonet Communications under the terms of the SignOnce IP License, the industry's first multi-vendor common license for FPGA-based IP. Visit www.xilinx.com/ipcenter/signonce.htm for more information on the SignOnce IP license.
About Paxonet
Paxonet Communications, Inc., designs, develops and markets silicon solutions for interworking metro networking technologies to SONET. Paxonet Communications offers the MetroConnect line of integrated circuits and the CoreEl line of specialized IP cores focused on the metro market. By offering a full range of interoperable ICs and IP cores, Paxonet enables customers to offer highly differentiated, low cost solutions with a quicker time to market. The company is privately held and employs 115 people. For more information about Paxonet Communications and its line of products, visit http://www.Paxonet.com.
Xilinx Online Resource for Metro Area Network Design
Xilinx eSP (www.xilinx.com/esp) is a proven resource for engineers, with four million visits since its introduction early last year. The latest segment on the eSP Web portal is dedicated to accelerating the development of metro area and edge access networking products. The site is a comprehensive resource, delivering a powerful array of solutions and information in a single location.
About Xilinx
Xilinx is the worldwide leader of programmable logic solutions. Additional information about Xilinx can be found at http://www.xilinx.com.
|
Related News
- MorethanIP releases the first combined 10GBase-R/W Core for 10 Gigabit Ethernet LAN and WAN PHY applications for FPGA
- Xilinx Showcases Industry's First FPGA-based 80Gbps Network Interface Card (NIC) and New Intel QPI Interface Implementation at IDF13
- Avago Technologies and Xilinx Streamline Design of 10 Gigabit Ethernet Systems Using FPGAs and Optical Interconnects
- Chelsio Communications Licenses Tensilica's Xtensa LX Customizable Dataplane Processor Core for 10 Gigabit Ethernet
- Xilinx and Brilliant Telecommunications Announce Industry's First Carrier-Class FPGA-Based Network Timing Solution for Next Generation Wired & Wireless Networks
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |