ARM Sizes Up Moore's Law
Memory wall, cost per transistor tackled
Rick Merritt, EETimes
12/7/2015 02:00 PM EST
SAN JOSE, Calif. — It’s getting harder and more costly to make chips smaller and faster, but there is still hope for advancing Moore’s Law, according to a keynote at the annual International Electron Devices Meeting (IEDM) in Washington D.C. this week. In a broad and balanced talk, a senior researcher at ARM detailed the variety of techniques and challenges ahead.
“The semiconductor industry will need to push equivalent Moore’s Law scaling through a broadening set of fronts…in an ‘all-of-the-above’ effort [that] will include more technology complexity, investment in technology-design optimizations, and ultimately technology-system optimizations,” Greg Yeric of ARM Research in Austin wrote in an IEDM paper.
E-mail This Article | Printer-Friendly Page |
Related News
Breaking News
- EXTOLL collaborates with BeammWave and GlobalFoundries as a Key SerDes IP Partner for Lowest Power High-Speed ASIC
- Celestial AI Announces Appointment of Semiconductor Industry Icon Lip-Bu Tan to Board of Directors
- intoPIX and EvertzAV Strengthen IPMX AV-over-IP Interoperability with Groundbreaking JPEG XS TDC Compression Capabilities at ISE 2025
- TeraSignal Demonstrates Interoperability with Synopsys 112G Ethernet PHY IP for High-Speed Linear Optics Connectivity
- Quadric Opens Subsidiary in Japan with Industry Veteran Jan Goodsell as President
Most Popular
- Certus releases radiation-hardened I/O Library in GlobalFoundries 12nm LP/LP+
- Mixel Announces the Opening of New Branch in Da Nang, Vietnam
- intoPIX and Nextera-Adeas Announce Latest IPMX Demo Design with JPEG XS on Compact FPGAs at ISE 2025
- EXTOLL collaborates with BeammWave and GlobalFoundries as a Key SerDes IP Partner for Lowest Power High-Speed ASIC
- Codasip and RED Semiconductor Sign Memorandum of Understanding to Develop AI Acceleration Technologies