MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
ARM Sizes Up Moore's Law
Memory wall, cost per transistor tackled
Rick Merritt, EETimes
12/7/2015 02:00 PM EST
SAN JOSE, Calif. — It’s getting harder and more costly to make chips smaller and faster, but there is still hope for advancing Moore’s Law, according to a keynote at the annual International Electron Devices Meeting (IEDM) in Washington D.C. this week. In a broad and balanced talk, a senior researcher at ARM detailed the variety of techniques and challenges ahead.
“The semiconductor industry will need to push equivalent Moore’s Law scaling through a broadening set of fronts…in an ‘all-of-the-above’ effort [that] will include more technology complexity, investment in technology-design optimizations, and ultimately technology-system optimizations,” Greg Yeric of ARM Research in Austin wrote in an IEDM paper.
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