Easy and secure solution to manage SoC power mode transitions from Dolphin Integration
Grenoble, France – February 1, 2016 -- Expectations of long battery life for ever more feature-packed applications require ultra low-power optimization to reduce overall power consumption.
Reaching the low-power consumption target for your SoC implies:
- To turn on/off different functions through clock gating and power-gating techniques for implementing power domains
- To manage the transitions between modes of these power domains
This previously complex task for SoC integrators is made straightforward thanks to Maestro™: a fast, easy and secure solution enabling the design of the Activity Control Unit (ACU) or Power Management Unit (PMU Logic). It serves to manage power island modes and mode transitions whatever the complexity of the SoC.
The Maestro™ network relies on different principles:
- Smart combination of soft and hard modules which structure and simplify the hierarchical design of the ACU or PMU Logic
-
More flexible and reusable than a custom “hand-made” interconnection and faster development than a full C/C++ solution
-
Application of the principle of subsidiarity which eliminates the risk of “conflict of modes” between shared power regulators and clock generators
-
- A dedicated control bus
-
Independent from the functional busses, thus authorizing the construction of the power island architecture over the functional block architecture
-
In addition to Maestro™, discover how to assemble and optimize your power management network thanks to the DELTA standard.
About Dolphin Integration
Dolphin Integration contributes to "enabling low-power Systems-on-Chip" for worldwide customers - up to the major actors of the semiconductor industry - with high-density Silicon IP components best at low-power consumption.
The "Foundation IP" of this offering involves innovative libraries of standard cells, register files and memory generators. The "Fabric IP" of voltage regulators, Power Island Construction Kits and their control network MAESTRO enable a flexible assembly with their loads. They especially star the "Feature IP": from high-resolution converters for audio and measurement applications to power-optimized 8 or 16 and 32 bit micro-controllers.
Over 30 years of experience in the integration of silicon IP components, providing services for ASIC/SoC design and fabrication with its own EDA solutions, make Dolphin Integration a genuine one-stop shop addressing all customers' needs for specific requests.
It is not just one more supplier of Technology, but the provider of the DOLPHIN INTEGRATION know-how!
The company strives to incessantly innovate for its customers’ success, which has led to two strong differentiators:
- state-of-the-art “panoplies of Semiconductor IP components” for high-performance applications securing the most competitive SoC architectural solutions,
- a team of Integration and Application Engineers supporting each user’s need for optimal application schematics, demonstrated through EDA solutions enabling early performance assessments.
Its social responsibility has been from the start focused on the design of integrated circuits with low-power consumption, placing the company in the best position to now contribute to new applications for general power savings through the emergence of the Internet of Things.
|
Dolphin Design Hot IP
Related News
- Dolphin Integration offers a live webinar on how to get an SoC power consumption under 0.5 uA in sleep mode
- INGChips selects Dolphin Integration's Power Management IP Platform for its ultra Low Power Bluetooth Low-Energy SoC in 40 nm eFlash
- Dolphin Integration sets up a large range of sponsored IPs at 55 nm to reduce SoC power consumption by up to 70%
- Dolphin Integration pushes SoC optimization to the next level with all risks managed
- Dolphin Integration's live webinar on Power, Performance and Area optimization during SoC physical implementation
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |