AMBA Parameter Configurable Multi-Channel DMA Controller (typically 1 to 256)
Intilop releases Network Security TOE Module for Altera and Xilinx FPGAs for their 10G & 40G Full TCP & UDP Offload Engines
MILPITAS, Calif. -- Feb 29, 2016 -- Intilop, Inc., a pioneer, most respected and recognized leader in providing Ultra-Low latency and Hyper Performance Complex Networking Protocol Accelerators like Full TCP, UDP, IGMP & other Mega IP Cores, Systems and Solutions since 2009, delivers yet another industry first: a full TCP and UDP Accelerator with Network Security capability which performs most of the functions of firewall and other monitoring functions at full line rate. In addition to full TCP/UDP offloading, this security module performs port filtering, blocking, monitoring and related functions in FPGA hardware thereby relieving CPU from these tasks and thus performing these functions in nanosecond speeds and with ultimate precision. The fact that CPU which gets bogged down under high traffic rates and sometimes misses some events, can be used for other application functions. So this is a win-win situation for both.
Ultra-fast and precise processing time of around 100 nanoseconds for this module including TCP and UDP with thousands of sessions at 10G sets the bar much higher for speed and performance powered by a 7+ year mature and proven TCP Protocol Compliant architecture
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UDP/IP Hardware Protocol Stack ![]() |
It was a highly significant achievement to develop this cutting edge technology rich architecture which implements Network Security module coupled with TCP and UDP Accelerators running at Full 10G Line rate. 40G soon to be released.
Working out of the box solutions with Choice of Cores implementing and this security module with 1K, 512, 256, 128, 32 and fewer concurrent TCP/UDP Sessions will be available in Q2 2016.
A sample of their TCP and UDP Accelerators can be found also at Altera and Xilinx websites:
- Altera: https://www.altera.com/solutions/partners/ip-partners/intilop.html
- Xilinx: http://www.xilinx.com/esp/datacenter/data_center_ip.htm
- Xilinx: http://www.xilinx.com/esp/datacenter/data_center_ip.htm
It not only offers ~100 ns latency and wire speed TCP performance, it also offers customization flexibility to network architects to design world-class system-level applications tailored to their specific needs.
The TOE's architecture is highly scalable, customizable and adaptable without compromising on low latency or performance. Intilop's product-line solutions are available in flexible FPGA/ASIC/SoC technologies which can easily accommodate diverse set of appliance maker's technical design specifications.
As a pioneer, Intilop was the first company to deliver a series of Full TCP Offload Engines on FPGAs in 2009. Their sub 100 ns latency MAC+TOE&UOE are considered a 'Gold Standard' by the industry experts.
The latency barrier of 100 nanoseconds and throughput of more than 1 G byte/s per port had been set by them since their first 10G Series of TCP engines in 2011.
About Intilop. Website: www.intilop.com
Intilop is a developer and pioneer in advanced networking silicon IP and system solutions, custom hardware solutions, SoC/ASIC/FPGA integrator and total system solutions provider for Networking, Network Security, storage and Embedded Systems. They offer silicon proven semiconductor IPs with comprehensive hardware and software solutions.
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