DINI Group announces full integration with EXOSTIV FPGA Debug Solution
March 21, 2016 -- DINI Group announces successful integration of the EXOSTIV FPGA Debug Solution with our Xilinx UltraScale and Virtex-7 series of ASIC Prototyping Products. The EXOSTIV solution enables FPGA debug at very high data rates into a large external memory (up to 8GB).
“We solved a difficult network test fixture bug using the bright orange EXOSTIV box, proving the value of the EXOSTIV solution,” said Mike DINI, president of DINI Group. “Our live TOE_IoT demonstration was crashing after 20 seconds of continuous operation. ChipScope Pro ILA and other debug solutions weren’t providing nearly enough memory depth. Network capture boards, which cannot handle 10GbE at >90% bandwidth were dropping packets. This lack of visibility made the debug process significantly more complicated, bordering on impossible. The EXOSTIV solution gave us deep debug memory depth at full bandwidth. We were able, in short order, to find and fix the Verilog bug in the test fixture.”
No custom hardware interfaces were required since the EXOSTIV box cables directly to SFP/QSFP sockets, which are native to DINI Group’s Virtex-7 and UltraScale products. The tools were easy to use and intuitive. The logic added internally to the FPGA by the EXOSTIV tools was minimally invasive and did not affect the timing of the design.
DINI Group is an established leader in large, FPGA-based boards, critical IP, and systems. DINI Group FPGA boards are used in large quantities for ASIC and SOC prototyping, low-latency trading, and high performance computing. From their corporate campus in La Jolla, California, DINI Group employees have supplied over fourteen billion ASIC gates.
Exostiv Labs (www.exostivlabs.com) is a division of Byte Paradigm sprl, a company incorporated in Belgium. Exostiv Labs is a trade name of Byte Paradigm sprl for solutions dedicated to FPGA and Programmable Logic.
|
Related News
- Exostiv Labs announces the availability of its 'EXOSTIV' solution for FPGA debug.
- Packet Plus and Dini Group partner to provide new approach to debug networking on logic emulation platforms
- The Dini Group Offers Stratix FPGA-based Development Platform
- Accellera's Security Annotation for Electronic Design Integration Standard 1.0 Moves Toward IEEE Standardization
- Arasan announces MIPI CSI IP for FPGA supporting full C-PHY 2.0 speeds
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |