Credo 16-nm 28G and 56G PAM-4 SerDes Now Available on TSMC FinFET Compact Process
Enables Customers to Leverage Advanced, Low-Power Process for Next-Generation Designs
MILPITAS, CA-- May 09, 2016 - Credo Semiconductor, a global innovation leader in Serializer-Deserializer (SerDes) technology, today announced the availability of its 28G and 56G PAM-4 SerDes transceiver IP on TSMC's 16-nm FinFET Compact (16FFC) process, enabling its growing customer base to take advantage of the low-power benefits of this advanced, new process in next-generation designs.
"Our close relationship with TSMC translates into a win-win for customers," said Bill Brennan, CEO of Credo Semiconductor. "As one of the first SerDes IP suppliers to port to this node, we enable the best of both worlds -- the combination of robust SerDes solutions with TSMC's advanced low-power 16FFC process. We look forward to supporting the needs of our mutual customers who are already adopting 16FFC for their next-generation designs."
"TSMC continues to expand 16-nm manufacturing options, providing customers with advanced technology to enable their end products," said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. "We have many customers that want both 28G and 56G SerDes IP solutions, and the availability of Credo's IP provides a proven solution for 16FFC high-performance computing applications."
Availability and Deliverables
The Credo 28G and 56G PAM4 SerDes IP is available now on the TSMC 16-nm FinFET Plus (FF+) and 16FFC processes. Deliverables include user and SoC integration guides; netlist; timing library; register map; Verilog, ATPG, and IBIS-AMI models; LEF views; Layout Versus Schematic (LVS) and Design Rule Check (DRC) reports.
Those interested in learning more about the company's current silicon and intellectual property engagement options, as well as future developments, should contact sales@credosemi.com.
About Credo Semiconductor
Credo is a leading provider of high performance, mixed-signal semiconductor solutions for the data center, enterprise networking and high performance computing markets. Credo's advanced Serializer-Deserializer (SerDes) technology delivers the bandwidth scalability and end-to-end signal integrity for next generation platforms requiring single-lane 25G, 50G, and 100G connectivity. The company makes its SerDes available in the form of Intellectual Property (IP) licensing on the most advanced processing nodes and with complementary product families focused on extending reach and multiplexing to higher data rates. Credo is headquartered in Milpitas, California and has offices in Shanghai and Hong Kong. For more information: www.credosemi.com.
|
Credo Semiconductor Hot IP
Related News
- Credo 16-nm 56G PAM-4 SerDes IP Now Available
- GUC and Credo Collaborate to Enable 16-nm FinFET+ Chip Development
- Credo Demonstrates Single-Lane 112G and 56G PAM-4 SerDes IP at TSMC OIP Forum
- Credo Demonstrates 56G PAM-4, 56G NRZ and 28G NRZ SerDes Technology at DesignCon
- Credo Tapes Out Industry-leading Serdes IP on 16-nm FinFET+ Process
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |