Inovys Announces Innovative ATE for DFT-based ICs
Platform optimizes use of DFT and BIST while lowering test costs
Pleasanton, CA, September 20, 2002 -- Inovys Corporation today announced the introduction and immediate availability of the Ocelot, a new DFT test system. The Ocelot has been specifically developed to support the economical testing of the full spectrum of integrated circuits, from low cost consumer devices to the most complex SoCs and microprocessors.
By taking advantage of on-chip test structures such as scan and BIST, the Ocelot tester reverses the trend requiring increasingly expensive ATE systems to test the most complex chips. With up to 1,536 signal pins, the Ocelot can be used to test high I/O SoC devices, or to test more than 32 devices in parallel. With its innovative Dynamic Data Matrix, the Ocelot provides the extended pattern depth and configuration flexibility required for large SoC designs without the high costs associated with large pattern memories. While providing scan data rates up to 50MHz, the Ocelot also offers special highly accurate clock pins that can support AC-scan strategies for at-speed testing of internal signal paths.
The Ocelot runs under Stylus, Inovys' innovative new software operating system that utilizes the IEEE1450 Standard Test Interface Language (STIL) as its programming language. Stylus is a major breakthrough for the design-to-test bottleneck. It links directly to the output of all major commercial ATPG products using the STIL test language. Another major benefit is the ability to link failure information directly back from the Ocelot to the ATPG diagnostic tools for gate level diagnosis of device defects. Since STIL is the native language to the Stylus OS , transfers of data from functional simulators and automatic test pattern generation programs are directly accepted without intermediate translation using third-party tools outside the normal design-to-test flow.
"This is the first in a series of products that answers the semiconductor industry's demand for a new cost/performance breakthrough in component test,", said Paul Sakamoto, CEO of Inovys. "While others have spent a lot of time and money developing cheaper versions of existing architectures, Inovys has taken advantage of the inflection point in the commercial success of DFT, BIST and the EDA tools that support them. By taking careful aim at the whole process of semiconductor design, validation, and test, Inovys engineers and scientists have produced a complete solution that is ten times more productive in terms of development time and cost of ownership. In addition, the resulting test methodology builds on many years of scan and BIST industry research to provide much better fault coverage than any other method."
The Inovys Ocelot test system is available in three configurations -- 512 pins, 1024 pins, and 1536 pins. It offers a wide variety and large number of power supply options to support a broad range of device types, as well as support of multi-site testing.
The most significant benefits to customers using Ocelot test solutions are lower testing costs, quicker test development efforts, and rapid feedback to design teams. With industry leading solutions for larger volume scan patterns, delay fault testing, BIST, and embedded memory, Inovys' innovative test systems address the test challenges of SoC, ASIC, datacomm, DSP, microprocessor, microcontroller, and other complex devices.
Ocelot shipments began in the second quarter of 2002. Pricing for the Ocelot is in the $300,000 to $600,000 range, depending upon pin count and options.
About Inovys Corporation
Inovys Corporation was founded to support the semiconductor industry's move to Design For Test (DFT) architectures with practical, economic, and scalable structured logic testing solutions. By offering a new generation of test system and software products, Inovys provides customers with substantial cost advantages when testing complex SoC's that incorporate DFT. Inovys' architects and EDA scientists have developed the first commercially available universal structured tester which combines seamless EDA-ATPG integration with closed loop fault feedback for continuing yield improvement. Inovys is headquartered in Pleasanton, CA, with offices in Austin, Texas. http://www.Inovys.com.
###
Ocelot and Stylus are trademarks of Inovys Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
|
Related News
- Enflame leverages Mentor's Tessent DFT solutions for innovative cloud AI chip targeting neural network training
- Graphcore leverages Mentor DFT solutions to speed time to market for innovative AI acceleration chip
- Barco Silex' FIPS-compliant DRBG IP integrated in innovative short-range wireless ICs of Dialog Semiconductors
- intoPIX to Showcase Innovative Automotive Imaging Solutions at AutoSens Europe 2024
- SiliconIntervention announces an innovative Fractal-D Audio Amplifier Family
Breaking News
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
Most Popular
E-mail This Article | Printer-Friendly Page |