7 µW always on Audio feature extraction with filter banks on TSMC 22nm uLL
Amba 3.0 aimed at larger SoCs
![]() |
Amba 3.0 aimed at larger SoCs
By Luke Collins, EE Times UK
September 23, 2002 (6:05 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020923S0003
ARM should unveil a new version of its Amba on-chip bus architecture in October. The bus has become a widely accepted interconnect standard for system-on-chip (SoC) design. Amba 2.0 was released in May 1999 and is so widely used that even competitors such as MIPS Technologies have taken it up. ARM is now working with partners to develop Amba 3.0. Simon Segars, executive vice- president of engineering at ARM, said: "We're looking at the bus requirements for large SoCs in future; what it takes to build a higher performance interconnect fabric." He says that as SoCs start using multiple processors on-chip, the interconnect may need to provide the sideband signals necessary for keeping maintaining system coherency. Segars says the Amba 3.0 architecture is also likely to include a lot of hierarchy and a partitioned bus structure to avoid wasting bandwidth by broadcasting all messages across the entire bus. Jonathan Morris, plat forms program manager at ARM, said: "It's fair to say a lot of activity has been going on working towards another turn of the spec." He says the new specification will continue the progress of ARM's on-chip bus, which has developed from the ARM System Bus (ASB) to Amba 2.0 in 1999, which introduced the ARM Hardware Bus (AHB). This was followed in 2001 by variants which included multi-layer AHB and AHB Lite. "AHB has done really well and established itself as a de facto standard," said Morris. He stresses that ARM is not abandoning AHB with the new Amba: "There will be a compatibility story with AHB. The new standard will move forward a long way, but we will provide the support and infrastructure so AHB and the new standard can co-exist." ARM is thinking about using Amba 3.0 to match the requirements of high-performance co-processors such as its MBX embedded 3D graphics cores. The company's roadmap for MBX implementations shows variants of the MBX core coupl ed with 64bit versions of Amba 3.0 as concepts for the first half of next year.
Related News
- ARM Announces AMBA 3.0 Program With Participation Of Over 25 Partners
- Denali Software First to Announce Verification IP for PCI Express 3.0 Designs
- Khronos Releases OpenGL 3.0 Specifications to Support Latest Generations of Programmable Graphics Hardware
- Intel Unveils Extensible Host Controller Interface Draft Specification to Support USB 3.0 Architecture
- PCI-SIG Announces PCI Express 3.0 Bit Rate for Products in 2010 and Beyond
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |