Andes Technology Corporation Announces Quick-Start Design Package That Significantly Reduces Time to Market of SoC Designs

Solution Reduces the Time Consuming and Error Prone Task of Creating and Verifying Glue Logic to Integrate Disparate Elements of an SoC Design

HSINCHU, TAIWAN-- June 07, 2016 -- Andes Technology Corporation, the leading Asia-based supplier of small, low-power, high performance 32-bit embedded CPU cores, today announced the Quick-Start Design Package, a complete solution that significantly reduces time to market for SoC designs. The package includes the new AndesCore™ N650 CPU IP, AndeShape™ AE100 Platform IP, and AndeSight™ IDE software development environment. The new compact N650 CPU provides the performance-efficiency needed for entry-level SoC, and the new Platform IP offers several highly-optimized peripherals and the bus fabric that SoCs require to surround and enable customer logic. By pre-integrating and pre-verifying processor, fabric, and peripherals, the package jump-starts customer's SoC projects with a solid foundation and reduces custom glue logic design teams need to create. Instead of hardwired control logic, customers can use software created with AndeSight IDE to debug the SOC and control the various peripherals.

"Time-to-market is a major concern for every SoC design and one task that slows a design progress is writing RTL code for developing standard IP blocks, integrating them, and spending 70 percent additional effort in verification," said Frankwell Jyh-Ming Lin, President of Andes Technology Corp. "The Quick-Start Design Package provides an optimized plug and play solution that saves effort developing common functions that are not providing any significant added value to their final design. Using software to control the peripheral elements reduces risk for SOC designs by eliminating the need to hardwire everything."

"By running control software on the new Andes N650 CPU IP, design teams reduce their risk considerably and shorten their silicon development schedule," said Charlie Hong-Men Su, Ph.D., Andes Technology CTO and Senior Vice President of R&D. "For example, it's a simple software revision to change the configuration of PCIe, DDR boot sequence, and other functions post-silicon. In addition to facilitating software development and optimization, the AndeSight IDE allows access to the entire system for chip-level debugging through the JTAG interface. By re-using the production-quality processor and peripheral controllers, and extensible bus fabric, the Quick-Start Design Package reduces design teams' risk of a silicon respin."

About the Quick-Start Design Package Solution

The individual elements of the Quick-Start Design Package -- new AndesCore™ N650 CPU IP, AndeShape™ AE100 Platform IP, and AndeSight™ IDE software development environment -- come with their own unique features. The new N650 CPU core is a 3-stage pipeline architecture with 16 general-purpose registers and multiply and divide instructions. The core delivers 25 percent better DMIPS/MHz performance and 40 percent better DMIPS/mW power efficiency than its competitive counterpart in the TSMC 90LP process.

The N650 CPU IP core has memory mapped I/O, a 32-bit wide AHB-Lite bus, up to 32 vectored interrupts, 4-priority nested interrupts, and power management instructions -- essential for power sensitive designs. The core comes with Embedded Debug Module, 2-wire Serial Debug Port and up to 8 breakpoints/watchpoints.

The new AE100 Platform IP features a new AHB Configurable Fabric with 24-bit address width and 32-bit data width. It supports up to 8 AHB masters, up to 30 AHB slaves and up to 31 APB slaves. Components of the fabric include AHB-Lite master multiplexer, AHB-Lite decoder and AHB-to-APB bridge. Other peripherals included are a Low-latency RAM Bridge, general purpose I/O (GPIO), watchdog timer, programmable interval timer and UART.

The AndeSight Eclipse-based IDE provides a fully functional Andes C and C++ integrated development environment that enables managed build system. It comes with a profiler, code coverage, code size analysis, chip profile, in-system programming, and advanced debugging. The tool chain includes compiler, assembler, linker, loader, libraries, and debugger. Also provided are a core simulator, pre-defined models of AndeShape™ SOC platform, and external plugin APIs.

Availability

The Quick-Start Design Package will be available the third quarter of this year. The Andes Quick-Start license includes the following:

• AndesCore™ N650 CPU IP
• AndeShape™AE100 Platform IP
• AndeSight™ IDE Software Development Environment

Also available is either a full-featured ADP-XC7 or a compact Andino F1 (Arduino-Compatible) optional development board along with Andes High-value Service and Support.

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