Renesas Adopts Cadence Interconnect Workbench to Accelerate Performance Analysis and Verification of On-Chip Interconnect
Performance analysis and functional verification time sped up by up to 50 percent compared to previous methodology
SAN JOSE, CA -- Jul 11,2016 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced that Renesas Electronics Corporation (TSE: 6723) has adopted the Cadence® Interconnect Workbench (IWB) to accelerate performance analysis and verification of their on-chip interconnects by up to 50 percent. Interconnect Workbench provided Renesas with a cycle-accurate performance analysis of interconnect throughout the system on chip (SoC) and micro controller design process by quickly identifying bottlenecks under critical traffic conditions, enabling Renesas to improve device performance and reduce time to market.
“As design complexity increases with more and more IP integrated on a single chip, accurate performance analysis of off-chip memory access and on-chip interconnect becomes more crucial,” said Toshinori Inoshita, senior manager, Elemental Technology Development Div. 1, Renesas System Design Co., Ltd. “Cadence Interconnect Workbench is a unique tool which allowed us to accurately monitor the performance of on-chip interconnect, dramatically improving turn around time for design architecture exploration. We’re planning to adopt this technology on additional new design projects at Renesas.”
Prior to adopting Cadence Interconnect Workbench, Renesas used a traditional methodology to develop performance verification environments and analyze the results. With their previous approach, they analyzed performance at IP, sub-system, chip design cycle independently. Interconnect Workbench, used in conjunction with the Cadence Incisive® Enterprise Simulator and vManager™ planning and metrics, enabled early detection of performance issues and early validation of system performance requirements on an integrated environment. Renesas also used Interconnect Workbench together with the Cadence Palladium® Z1 Enterprise Emulation Platform to accelerate the application-level performance analysis and verification with emulating software loads on their design.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.
|
Cadence Hot IP
Related News
- Cadence Announces Availability of Interconnect Workbench for Performance Analysis and Verification of ARM-Based SoCs
- Sonics Adopts Cadence JasperGold Apps Formal Verification for On-Chip Network IP Development
- Synopsys PrimeTime Advanced On-chip Variation Analysis Enables Renesas to Accelerate Timing Closure at 65-nm and Below
- Cadence Introduces EMX Designer, Delivering More Than 10X Increased Performance for On-Chip Passive Component Synthesis
- ARM System IP boosts SoC performance from edge to cloud
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |