Amba on-chip bus is core link for Synopsys
![]() |
Amba on-chip bus is core link for Synopsys
By Chris Edwards, EE Times UK
October 2, 2001 (12:12 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010928S0019
Synopsys has decided to adopt ARM's Amba on-chip bus as the favoured way to link the main cores in its DesignWare library of intellectual property (IP). The California-based EDA firm plans to use Amba to make it easier to incorporate 'star IP' cores, such as processors, in DesignWare. But the company has decided to stick with its existing yearly subscription model for DesignWare by only including models for ARM, MIPS and other processors, not the cores themselves. Customers will have to negotiate licensing terms with IP suppliers, although Synopsys will provide design views for early evaluation. Phil Dworsky, director of marketing and business development for Synopsys, said: "There are three partners who are full partners: Infineon, mips and NEC. We are working with them to make their cores fully reusable. We are packaging them to make them work with the [Amba] on-chip bus. Once the licence is secured, we will deliver the RTL [hardware design]." Synopsys will provide ARM's simulation models but the UK processor cores company is only 'endorsing' Synopsys' approach. Dworsky says Synopsys will port larger cores, such as PCI and PCI-X bus interfaces, to Amba: "We have a separate development on Amba subsystems. They are peripherals such as timers, interrupt controllers and Uart." The company is looking for other suppliers "with IP complementary to DesignWare" to join the programme. Synopsys will support version 2.0 of the Amba specification initially. Cores for the switch-fabric version, multi-layer Amba hardware bus (AHB), and AHB Lite, will arrive in mid-2002.
Related News
- Synopsys Introduces Lower Power, High-Performance Architecture for AMBA 3 AXI On-Chip Interconnect
- TEMENTO SYSTEMS announces the introduction of a Bus Trace Analyzer for On-Chip AMBA and ARM processor-based Verification
- NetSpeed Systems to Bring its Next-Generation Cache Coherency to Enterprise Market with Extended ARM License
- Synopsys Introduces Industry's First On-Chip Memory Test and Repair Solution for Embedded Flash
- Synopsys PrimeTime Advanced On-chip Variation Analysis Enables Renesas to Accelerate Timing Closure at 65-nm and Below
Breaking News
- Siemens delivers certified and automated design flows for TSMC 3DFabric technologies
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |