Microsoft Gives Peek at HoloLens Chip

EE Times
8/23/2016 08:40 AM EDT

CUPERTINO, Calif. — Microsoft gave the first peek inside the custom vision processor it designed for its HoloLens augmented reality headset. The chip handles a trillion pixel-operations/second in a power budget lower than the 4W Intel Atom-based Cherry Trail SoC that acts as its host processor.

The HoloLens processing unit (HPU) fuses input from five cameras, a depth sensor and motion sensor, compacting and sending it to the Intel SoC. It also recognizes gestures and maps environments including multiple rooms.

Microsoft described the guts of HoloLens earlier this year, but has not until now publicly detailed its HPU. The company evaluated merchant computer-vision chips including those from Movidius but found none that handled all its algorithms at its performance, latency and power targets.

The TSMC 28nm chip packs 24 Tensilica DSP cores and 8 Mbytes cache into a 12x12mm package with 65 million transistors. A GByte of LPDDR3 is included in the HPU’s package.

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