Mixel MIPI D-PHY IP Integrated into Lattice's CrossLink Low Power pASSP

First Bridge Supporting 12 Gbps of Aggregate Bandwidth Leverages Mixel MIPI D-PHY

San Jose, CA – September 7^th, 2016 - Mixel^®, the leader in mobile mixed-signal intellectual property (IP), and Lattice Semiconductor (NASDAQ: LSCC), a leading provider of customizable smart connectivity solutions, today announced that Mixel’s complete MIPI^® solution has been successfully integrated into Lattice Semiconductor’s recently announced CrossLink^TM solution, the industry’s first programmable bridging device that resolves interface mismatches between mobile application processors, image sensors and displays. The new CrossLink bridge combines the flexibility and fast time to market of an FPGA with the power and functional optimization of an ASSP to create a new product class called programmable ASSP (pASSP™). This solution, which is now going into production, integrates Mixel’s high performance, low power Universal MIPI D-PHY^SM, implemented in UMC’s 40nm process to achieve first silicon success.

The Mixel IP integrated into the CrossLink product is an ultra-low power MIPI D-PHY with many differentiating features, which include power-switching to drastically reduce leakage current, elaborate power on control circuitry, enabling intermediate power down states with faster power up responses, a small footprint, and a highly programmable parallel interface.

“In our market segment, ultra low power and a small footprint are critically important. After our in-depth evaluation, we chose Mixel as our MIPI IP provider because its mature solution met our stringent requirements,” said Sherif Sweha, corporate vice president of research and development at Lattice Semiconductor. “Mixel has been a valuable partner to us and we’re looking forward to continued collaboration. Their support from project start to manufacturing transfer has been world-class.”

“It’s rewarding that the first FPGA to integrate MIPI D-PHY 1.1 with a 12 Gbps aggregate bandwidth is now going into production with Mixel’s MIPI IP. By working closely with Lattice Semiconductor, the experts in delivering low power FPGAs, we have achieved further reduction in both active and leakage current of the MIPI PHY. We’re proud to achieve this while living up to our motto of, ‘First-time success is the rule, no exceptions,’” said Ashraf Takla, Mixel’s President and CEO.

Lattice Semiconductor and Mixel will be demonstrating multiple platforms using CrossLink technology at the MIPI Alliance Developers Conference in Mountain View, CA on September 14-15, 2016.

About Mixel^®:

Mixel is the leader in mixed-signal mobile IPs and offers a wide portfolio of high-performance mixed-signal connectivity IP solutions. Mixel’s mixed-signal portfolio includes PHYs and SerDes, such as Mobile PHYs (MIPI^® D-PHY ^SM, M-PHY^®, and LVDS), general purpose Transceivers, and high-performance PLL and DLL IP cores.

For more information contact Mixel at info@mixel.com or visit www.mixel.com.

About Lattice Semiconductor:

Lattice Semiconductor (NASDAQ: LSCC) provides smart connectivity solutions powered by our low power FPGA, video ASSP, 60 GHz millimeter wave, and IP products to the consumer, communications, industrial, computing, and automotive markets worldwide. Our unwavering commitment to our customers enables them to accelerate their innovation, creating an ever better and more connected world.

For more information about Lattice please visit www.latticesemi.com.

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