Wi-Fi 6 (ax)+BLEv5.4+15.4 Dual Band RF IP for High-End Applications.
Asiczen Releases its CAN Verification IP
October 4, 2016 -- Asiczen Technologies announces the release of its UVM based CAN verification IP. azCAN is fully compliant with CAN specification 2.0. azCAN is a UVM based verification component (UVC) that can be used by IP and SOC makers to test their CAN interface design effectively and quickly.
This easy-to-use UVC can be easily integrated to any UVM based environment and can be used to generate a variety of scenario without much effort. CAN is a multi-master serial bus standard for connecting Electronic Control Units [ECUs] also known as nodes. Two or more nodes are required on the CAN network to communicate.
The complexity of the node can range from a simple I/O device up to an embedded computer with a CAN interface and sophisticated software. The node may also be a gateway allowing a standard computer to communicate over a USB or Ethernet port to the devices on a CAN network.
|
Related News
- Asiczen Releases its SMBus Verification IP
- Asiczen Releases its APB Verification IP
- AMIQ EDA Releases Major Customer-Focused Product Line Update
- New Wave DV Releases Two New SOSA-Aligned 3U VPX ACAP (FPGA) Modules
- Imperas releases new updates, test suites, and functional coverage library to support the rapid growth in RISC-V Verification
Breaking News
- intoPIX Powers Ikegami's New IPX-100 with JPEG XS for Seamless & Low-Latency IP Production
- Tower Semiconductor and Alcyon Photonics Announce Collaboration to Accelerate Integrated Photonics Innovation
- Qualcomm initiates global anti-trust complaint about Arm
- EnSilica Agrees $18m 7 Year Design and Supply ASIC Contract
- SiliconIntervention Announces Availability of Silicon Based Fractal-D Audio Amplifier Evaluation Board
Most Popular
- Qualcomm initiates global anti-trust complaint about Arm
- Siemens acquires Altair to create most complete AI-powered portfolio of industrial software
- Alphawave Semi Reveals Suite of Optoelectronics Silicon Products addressing Hyperscaler Datacenter and AI Interconnect Market
- EnSilica Agrees $18m 7 Year Design and Supply ASIC Contract
- Rapidus Announces Strategic Partnership with Quest Global to Enable Advanced 2nm Solutions for the AI Chip Era
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |