MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
TSMC Staffing R&D for 3nm Process
Julien Happich, EETimes
10/4/2016 10:46 AM EDT
PARIS — Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) will actively develop 5-nanometer process technology, while dedicating between 300 and 400 R&D personnel in developing a 3-nanometer process, ultimately aiming at the 1-nanometer manufacturing process, reports Taiwanese magazine CTimes.
In an interview, Dr. Mark Liu, President and Co-Chief Executive Officer of TSMC, said the company will use its three-dimensional stacked architecture technology to break the limitation of Moore's law and move toward the 3nm manufacturing node.
Liu stressed that TSMC has established the complete ecosystems with the intellectual property, automation solutions and equipment providers, and will continue to invest in technology development and research, and to make Taiwan become the strongest fortress in the global semiconductor industry.
E-mail This Article | Printer-Friendly Page |
|
Related News
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- Sofics releases its ESD technology on TSMC 3nm process
- MediaTek Successfully Develops First Chip Using TSMC's 3nm Process, Set for Volume Production in 2024
- Synopsys Accelerates Advanced Chip Design with First-Pass Silicon Success of IP Portfolio on TSMC 3nm Process
- TSMC Japan 3DIC R&D Center Completes Clean Room Construction in AIST Tsukuba Center
Breaking News
- GUC Joins Arm Total Design Ecosystem to Strengthen ASIC Design Services
- QuickLogic Announces $6.575 Million Contract Award for its Strategic Radiation Hardened Program
- Micon Global and Silvaco Announce New Partnership
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
Most Popular
- GUC Joins Arm Total Design Ecosystem to Strengthen ASIC Design Services
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- VeriSilicon unveils next-generation high-performance Vitality architecture GPU IP series
- SafeNet Reiterates Guidance and Clarifies Revenue Assumptions
- Micon Global and Silvaco Announce New Partnership