English
EE Slashes CPU Design Cost
4.5B transistor tapeout for less than $1M
Rick Merritt, EETimes
10/5/2016 00:01 AM EDT
SAN JOSE, Calif. — One engineer, with a little help from contractors, taped out in less than a year a 4.5 billion transistor chip that on paper kicks out more GFlops/mm2 than Intel’s top-end processors. Andreas Olofsson says the Adapteva Epiphany-V shows a hundred-fold efficiency gain in the way chips can be designed.
Some of Olofsson’s gains come from the fact the research chip employs a single core replicated 1,024 times and much of the IP is an evolution from prior designs. Nevertheless, the chip used a state-of-the art 16FF+ TSMC process and fits into a compact 117mm2.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related News
- Lattice Slashes Cost, Speeds Development of Mobile Devices With New Plug-In-&-Go USB iCEstick FPGA Evaluation Kit
- ChipX Slashes Cost of System-on-Chip Development With Hybrid ASIC
- MIPS Releases P8700, Industry's First High-Performance AI-Enabled RISC-V Automotive CPU for ADAS and Autonomous Vehicles
- ADTechnology Partners with Arm, Samsung Foundry, and Rebellions on AI CPU Chiplet Platform
- RaiderChip brings Meta Llama 3.2 LLM HW acceleration to low cost FPGAs
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards