EE Slashes CPU Design Cost

4.5B transistor tapeout for less than $1M

Rick Merritt, EETimes
10/5/2016 00:01 AM EDT

SAN JOSE, Calif. — One engineer, with a little help from contractors, taped out in less than a year a 4.5 billion transistor chip that on paper kicks out more GFlops/mm² than Intel’s top-end processors. Andreas Olofsson says the Adapteva Epiphany-V shows a hundred-fold efficiency gain in the way chips can be designed.

Some of Olofsson’s gains come from the fact the research chip employs a single core replicated 1,024 times and much of the IP is an evolution from prior designs. Nevertheless, the chip used a state-of-the art 16FF+ TSMC process and fits into a compact 117mm².

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