English
Valiosys links with TNI to 'lead' design and verification
 |
Valiosys links with TNI to 'lead' design and verification
By Peter Clarke, EE Times UK
September 27, 2001 (10:59 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010927S0032
Continuing consolidation in the French EDA industry has created what is claimed to be one of the world's leading design and verification players. In June, Valiosys merged with Arexsys. Now Valiosys has merged with Techniques Nouvelle d'Informatique (TNI), creating TNI-Valiosys. This has resulted in a 70-person company with both product and expertise spanning formal verification, hardware-software co-design and computer aided software engineering. Marc Frouin, previously CEO of Valiosys, becomes CEO of the new company, while TNI's co-founders become general managers. Frouin says an extra $4m has been invested into TNI-Valiosys by a team of venture capital firms based around those that originally backed Arexsy and Valiosys. TNI-Valiosys claims to have expertise ranging from real-time object-oriented development languages, modelling, formal validation and code generation to system-on-chip design. The company's products include imProve-H DL, which combines elements of model checking and formal theorem proving, and is based on formal verification technology known as "linear programming validation". Since acquiring Arexsys, Valiosys has been shipping the Arexsys-developed ArchiMate, a design tool it claims can take a chip design from an early functional description to synthesisable HDL code. It supports C and VHDL languages, with SystemC 2.0 support expected. TNI's product line includes design tools for real-time and distributed systems software and design tools for industrial control command systems. Frouin said: "TNI's expertise in critical software engineering strengthens Valiosys' position as a supplier of semiconductor design and verification technologies, and enables us to become one of the world's leading companies in the field. There is an opportunity to bring the system application knowledge down to the co-design and semiconductor knowledge." Peter Clarke is European correspondent for US sister n ewspaper EETimes.
Related News
- Calypto's Industry Expands Lead in ESL Verification with Latest SLEC Release
- TNI-Valiosys and TransEDA Join Forces to Better Serve the Verification and Validation Markets
- TNI-Valiosys and Verisity Join Forces to Deliver a Combined Static and Dynamic Verification Sub-flow; Integration Boosts the Quality and Time-to-Market of SOC Designs
- TNI and Valiosys develops system level formal verification and co-design solutions.
- Kevin O'Buckley to Lead Foundry Services at Intel
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |