Adelante Unveils Application-Specific Open SoC DSP Platform Strategy

Open SoC DSP Offering to Include Customizable DSP Cores plus Application Specific IP and DSP Sub-system.

OCTOBER 3, 2001, COMMUNICATION DESIGN CONFERENCE, SAN JOSE, CA - Adelante Technologies announced today that it will offer complete SoC DSP platforms, including a variety of customizable, programmable DSP cores, highly optimized application specific co-processors, a comprehensive software development environment to port application code to the platform, and an integrated HW/SW co-verification and emulation environment. In addition, the company will offer selected customers development tools for the creation of "proprietary" application specific instructions, accelerators, and co-processors.

Unlike any other DSP core offering, Adelante's DSP platforms will be available with a complete DSP sub-system, including DMA, debug, BIST, JTAG, and efficient bus interfaces to RISC controllers, memory, peripherals and I/O.

Adelante Technologies' DSP platforms will be based on the R.E.A.L. DSP technology acquired from Philips Semiconductors at the time the company was formed. To date, more than 100 million R.E.A.L. DSP cores have been integrated in a wide variety of wireless, multimedia and networking applications that include GSM, CAR radios, DECT, voice control, DTAM, MP3, digital servo, VoIP and digital audio. 

Adelante's first DSP platform family will be introduced in 2002 - Adelante's Chief Operating Officer, Herman Beke explained, "The products of the future, such as digital video, 3G phone and wireless LANs, require massive amounts of digital signal processing. The processors in them will have to execute many millions of operations per second and handle vast amounts of data. While they are doing this, they will not be allowed to consume a lot of power. Nor can they cost very much.

"An additional, but equally important, consideration is that of system integration. Even the most highly optimized DSP core does not operate in a vacuum. It must interface to its DMA engine, external memory, RISC processors, I/O, and peripherals. As DSP cores become more complex, assembling and verifying the DSP sub-system within the SoC platform design context also becomes incredibly more complex. The days of the "shrink-wrapped", naked DSP cores are over. DSP core vendors will have to offer a complete embedded SoC DSP solution. In order to minimize time-to-market for their customers, they also will have to join their customers in the design of the SOC.

"Addressing these issues is the mission of Adelante Technologies. We believe that, by combining the open SOC DSP Core and DSP Subsystem of Philips and the automatic co-processor synthesis methodology and design services of Frontier Design, we are well on the way to achieving that goal."

Highly Customizable Cores - The DSP processors in Adelante's families of DSP platforms are based on Philips Semiconductors' family of R.E.A.L DSP cores. The next generation cores being developed by Adelante will include VLIW instructions with code compaction, two or more multipliers and four or more ALUs. They will offer a variety of customization and optimization options that include: application specific instructions, application specific hardware execution units, and tightly connected complex co-processors.

Application specific instructions exploit the parallelism in the processor architecture. The processors initially planned will have 16- or 24-bit data-words and 16-bit instruction words. Written by the designer or provided by Adelante, application specific instructions are also 16-bits wide, but use a patented technique to access the full set of VLIW operations from a look-up table in the core. The VLIW instructions are then executed in parallel mode. For example, the calculation of a Viterbi butterfly that takes four standard instructions to execute, can be coded using an application specific instruction that combines the core's processing resources in parallel to create a single VLIW instruction that executes in a single clock cycle. Multiple sets of application specific instructions can be dynamically loaded and activated for different application domains.

Rob Woudsma, Adelante's Chief Technology Officer, summarized "The use of application-specific instructions effectively combines the intrinsic parallel processing power of this VLIW architecture with the high code density of a compact 16-bit instruction set. In SoC applications, this powerful feature translates into very competitive, low-cost, low-power DSP implementations, while not giving in on high functional performance."

Application specific execution units are customized hardware extensions to Adelante's cores that execute specific functions in a single cycle. Application specific execution units can be used to implement combinations of operations that are executed by one or more additional shifters, ALUs, MACs, ACUs, or fast multipliers. They can be used to accelerate complex, compute-intensive functions such as MPEG, Viterbi, ADPCM or MP3. The application specific execution units, once included in the DSP core, are exploited by the designer with application specific instructions.

Complex co-processors - The highest level of application specific optimization can be gained by using an Adelante co-processor that is tightly connected to Adelante's DSP core. Co-processors execute complete sub-functions such as G7XX, MPEG4, and turbo coding. The co-processor executes its function in parallel to the Adelante DSP core, as well as with cores from other vendors.

Buy or Build Accelerator Libraries - Adelante will offer pre-packaged libraries of application specific instructions, application specific execution units and co-processor IP cores. Certain customers will also be allowed to generate their own additional application specific execution units and co-processors. Adelante will offer them the A|RTTM Designer methodology to expedite and optimize this process.

Complete DSP Sub-system - Uniquely, DSP cores from Adelante Technologies will be available with the complete DSP sub-system, including DMA, debug, BIST, JTAG, and bus interfaces to external RISC processors, DSP peripherals, embedded memory and I/O.

Interactive Development Environment With Compact C-compilation - All Adelante's SoC DSP Platforms will come with a fully graphical interactive development environment, including C-compilation and a multi-core debug facility. The software development environment fully exploits the intrinsic quality of the hardware platforms and thus offers excellent code density. For example, using "out-of-the-box" code for G.721, Adelante achieved compiled code size of only 1700 words, with no hand-optimizing.