Smartlogic Announces PCI Express Multichannel DMA IP Core optimized for Video Streaming

The new release of the Multichannel DMA IP Core for PCI Express® contains important features that greatly simplify the DMA transmission of several independent videodatastreams and supports the Xilinx 7 and Ultrascale FPGAs.

Holzgerlingen, Germany -- October 13th , 2016 – Smartlogic today announced the immediate availability of the new 4.0 Release of the Multichannel DMA IP Core for PCI Express®.

Outstanding feature of the new version is the simultaneous transmisson of up to 16 Streaming Channels in separate memory buffers of the host system. The User can use his own clockdomain and can adjust the datawidth for each channel. The events "Start of Frame", "End of Frame" and "End of line" are supported and control the storage in memory and can be used as interrupt triggers.

"The Smartlogic DMA IP Core for PCI Express greatly simplifies the connection of many independent videodatastreams", said Thomas Zerrer, CEO of Smartlogic. "We integrated parametrizable Data FIFOs in the datachannels of the IP in order to realize a priority scheme. This prevents high priority channels from being blocked by low priority channels."

The IP Core though does not only target the growing field of streaming applications. Due to the integrated DMA Read Module it is possible to realize Co-Processor applications, where the IP Core reads data from a datasource, then processes the data and writes it to the target.

The IP Core is also featuring the continuous monitoring of Signal Integrity, where CRC Errors on the PCIe Link are permanently counted. With this feature it is possible to detect soldering problems during productional tests. Security critical applications greatly benefit from this feature.

The new 4.0 Release is the beginning of a new product launch until the end of the year. Besides the long awaited support for Altera FPGAs, there will be a new Multifunction Extension for the Xilinx Hard IP, that allows to build true PCI Express Multifunction Devices within the Xilinx Artix and Kintex Devices without the need for a costly Soft IP.

Learn More:

Visit Smartlogic’s Website to download the 4.0 datasheet.

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