LSI Logic DDR interface core delivers up to 400Mb/s for high-speed DDR SDRAM applications
- Pre-designed interface core now available to simplify ASIC interfaces to DDR SDRAM
- Ideal for storage, computing, printer, and communications applications
MILPITAS, Calif., October 8, 2002 – LSI Logic Corporation today announced the general availability of its double data rate (DDR) SDRAM interface core. The LSI Logic DDR core, which greatly simplifies ASIC design for interfaces to DDR SDRAM memory, reaches data rates of up to 400 Megabits per second per pin at 200 MHz. This innovative, easy-to-integrate core reduces development time and design complexities. The DDR cores are ideally suited for storage, computing, printer and communications applications.
"Without the LSI Logic DDR core, an ASIC designer must design an interface that meets the tight timing requirements of DDR SDRAM, a challenging, time-consuming and costly effort. By using this pre-defined and pre-verified core, our customers will realize shorter development times, lower system costs and greater performance and reliability," stated Dave Jones, vice president and general manager of LSI Logic's Storage and Computing ASIC Division. "Demand is high for reliable interfaces between ASICs and high-speed DDR SDRAM. LSI Logic is delivering this valuable technology today, and we'll continue to offer next generation cores as customer needs evolve."
"LSI Logic provided HP with a complete, pre-verified DDR core that handled the critical timing in our ASIC DRAM interface," said Rick Klaus, senior design engineer, HP Imaging and Printing Group. "This enabled us to more rapidly complete our memory controller design."
The LSI Logic DDR interface core is available in the company's G12™ 0.18-micron and Gflx™ 0.11-micron process technologies, leveraging LSI Logic's extensive expertise in high performance I/O interfaces. The core provides a robust physical layer interface to high performance DDR SDRAM memory and uses a simple ASIC side interface. The ASIC designer has the flexibility to use a performance-optimized DDR memory controller from LSI Logic, an internal memory controller or a third party memory controller.
"The G12 DDR Core has been fully characterized with test chips and in several of our customer's products, meeting the 200 MHz specification with plenty of margin," said Khanh Le, vice president of High Speed Interface Engineering at LSI Logic.
The DDR SDRAM core is offered as a hardmac with pre-verified layout and timing. The 8-bit-wide core can be used in parallel to scale up to 32-bit, 64-bit and higher bus widths, giving designers the greatest flexibility. Based on today's industry standards, the core allows designers to read and write DDR SDRAM memories in point-to-point and Dual In-Line Memory Module (DIMM) configurations.
The DDR cores are part of the LSI Logic CoreWare® design program, an extensive library of pre-designed and pre-verified cores that can be easily integrated with customer-designed logic. The CoreWare program reduces development time and overall system cost while increasing system performance and reliability. Customer designs with the LSI Logic DDR cores are already underway.
The DDR interface core is also available in our recently-announced RapidChip semiconductor platform for fast SoC designs.
About LSI Logic Corporation
LSI Logic Corporation (NYSE: LSI) is a leading designer and manufacturer of communications, consumer and storage semiconductors for applications that access, interconnect and store data, voice and video. In addition, the company supplies storage network solutions for the enterprise. LSI Logic is headquartered at 1621 Barber Lane, Milpitas, CA 95035, http://www.lsilogic.com.
|
Related News
- LSI Logic Simplifies High-Speed Serial Interface Design with Expanded Rapidchip Xtreme Family of Platform ASICs
- LSI Logic Unveils Industry's Highest Speed DDR-2 SDRAM Physical Layer Memory Interface
- LSI Logic Hypertransport physical interface core power high-speed data transfer rates
- LSI Logic first with Serial ATA 1.0 ASIC implementation - expands high-speed interface portfolio
- LSI Logic extends leadership in high-speed serial interconnect with two GigaBlaze 0.11-micron multi-gigabit transceiver cores
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |