M31 Receives TSMC's 2016 Partner of the Year Award for Specialty Technology IP
Hsinchu, Taiwan – October 27th, 2016 -- M31 Technology Corporation received TSMC’s “2016 Partner of the Year Award” for Specialty Technology IP at TSMC’s Open Innovation Platform Ecosystem Forum on September 22, 2016 in San Jose California.
M31 has been a member of TSMC’s IP Alliance Program since 2012 and has developed various IP for TSMC processes, ranging from 180nm to 16nm that have passed the TSMC9000 quality assessment. These IP are focused on SRAM Compilers, Standard Cell Libraries, and General Purpose Input/Output (GPIO) to enable SoC designers to achieve their designs with lower power consumption, higher performance, and compact size.
In TSMC 28HPC+, 40EF, and 55ULP process technologies, M31 has developed fundamental IP specifically for IoT and wearable applications with its low power consumption characteristics. In addition, M31’s IP in TSMC 40HV, 110HV, and 152GPIIA process technologies are suitable for chips designed for LCD/LED driver and PMIC power management functions. With the advantages of high voltage (HV) and Bipolar CMOS DMOs (BCD) process technologies, these IP are the enablers for highly integrated and power efficient chips, managing the power supply to meet the needs of TV, telecommunication equipment and automotive visual display products.
“TSMC thanks M31 for its many contributions,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. "With the support of an unmatched design ecosystem, customers can develop their products – such as intelligent devices and power management devices – running in different voltage and power conditions.”
"It’s our honor to receive this Specialty Technology IP Partner Award from TSMC. This award demonstrates that M31 has been capable of providing IP solutions in multiple TSMC technology platforms," said H.P. Lin, Chairman of M31 Technology. "M31 has developed the specialty IP with its exceptional low power consumption in TSMC’s process technology. In the future, M31 will continue its IP development and validation in advanced process technologies to provide distinctive silicon IP to the worldwide chip design community.”
In addition to the fundamental IP, M31 also collaborates with TSMC to develop a series of high-speed interface IP, including MIPI, USB, PCIe and SATA, in order to meet customer requirements for various applications.
|
M31 Technology Corp. Hot IP
USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm ...
PCIe 4.0 PHY in TSMC(6nm,7nm,12nm,16nm)
MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and ...
MIPI D-PHY RX/TX v1.1 / v1.2 IP in TSMC (12/16nm, 28nm, 40nm, and 55nm process)
SerDes PHY IP(12nm, 14nm, 22nm, 28nm)
Related News
- M31 Receives TSMC's 2018 Partner of the Year Award for Specialty Process IP
- M31 Technology Receives 2020 TSMC OIP Partner of the Year Award for Specialty Process IP
- M31 Technology Won TSMC's 2019 Partner of the Year Award for Specialty Process IP
- Dolphin Integration receives TSMC's Open Innovation Platform 2015 Partner of the Year Award for Specialty IP
- Dolphin Integration receives TSMC's Open Innovation Platform 2014 Partner of the Year Award for Specialty IP
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |