ARM Fellow Surveys Moore's Law
Researcher remains upbeat despite challenges
Rick Merritt, EETimes
10/27/2016 02:00 AM EDT
SANTA CLARA, Calif. — Chip makers used to laugh at Greg Yeric’s idea for boosting Moore’s law. It was too difficult and risky. Now they’re researching it.
The experience of the ARM fellow is another sign that engineers are leaving no stone unturned in their efforts to keep making smaller, faster chips. Yeric expressed optimism for several more generations of semiconductors although he was frank about the challenges ahead, speaking in an interview after a keynote talk at the ARM Tech Con here.
Traditional cost reductions are coming more slowly as power savings and performance increases become harder to find, Yeric said in his talk. Engineers need to scan a wide field of new materials and processes and manage an increasing pace of change affecting the whole supply chain, he said.
E-mail This Article | Printer-Friendly Page |
Related News
Breaking News
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- YorChip announces patent-pending Universal PHY for Open Chiplets
- PQShield announces participation in NEDO program to implement post-quantum cryptography across Japan
Most Popular
- Qualitas Semiconductor Signs IP Licensing Agreement with Edge AI Leader Ambarella
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura's Cyberthreat Intelligence Tool
- Altera Launches New Partner Program to Accelerate FPGA Solutions Development
- Alchip Opens 3DIC ASIC Design Services
- Electronic System Design Industry Posts $5.1 Billion in Revenue in Q3 2024, ESD Alliance Reports