IPrium releases 40G I.3 Encoder/Decoder for DWDM systems
TOMSK, Russia, December 27, 2016 - FPGA intellectual property (IP) provider IPrium LLC (www.iprium.com) today announced that it has expanded its family of Super-FEC IP products with a new OTU3 40G I.3 BCH Codec IP Core for the G.975.1 standard.
The IP Core is a complete Encoder and Decoder module and is optimized for 40-46 Gbit/s optical communication systems. The redundancy ratio of the super-FEC code is 6.69% and the net coding gain is 9.26 dB for output BER=1e-16.
The 40G I.3 BCH Codec has been silicon-proven and is compliant with ITU-T G.975.1 Standard (as of 02/2004) "Forward error correction for high bit-rate DWDM submarine systems. Appendix I. Super FEC schemes I.3 Concatenated BCH super FEC code".
The IP Core provides turnkey single-chip solution that can be used in low-cost high-throughput applications.
Pricing and Availability
The 40G I.3 BCH Codec IP Core is available immediately in synthesizable Verilog or optimized netlist format, along with synthesis scripts and simulation test bench with expected results.
For further information, product evaluation, or pricing, please visit the IP Core page:
About IPrium LLC
IPrium Modem IP Cores allow designers of communication equipment to rapidly and cost-effectively develop and verify their systems. IPrium offers FPGA and ASIC IP Cores for high-quality modems to customers worldwide. Visit IPrium at www.iprium.com.
|
IPrium LLC Hot IP
Related News
- IPrium releases 40G LDPC I.6 Encoder/Decoder for DWDM systems
- IPrium releases 100 Gbps Polar Encoder and Decoder
- IPrium releases CCSDS TM Telemetry AR4JA LDPC Encoder and Decoder
- IPrium releases IEEE 802.11n/ac/ax LDPC Encoder and Decoder
- IPrium releases CCSDS TC Telecommand LDPC Encoder and Decoder
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |