Intel Unveils 10, 22nm Processes
Transistor-density metric proposed
Rick Merritt, EETimes
3/28/2017 08:45 PM EDT
SAN FRANCISCO – Intel will start making 10nm chips this year it claims will lead the industry in transistor density using a metric it challenged rivals to adopt. Separately, it announced a 22nm low-power FinFET node to compete for foundry business with fully depleted silicon-on-insulator (FD-SOI) from rivals such as Globalfoundries.
At 10nm, Intel will pack 100.8 million transistors per square millimeter. It estimated 10nm foundry processes now in production from TSMC and Samsung have about half that density.
Intel’s metric averages density of a small and a large logic cell. Specifically, it uses a two-input NAND cell with two active gates and a scan flip-flop cell with as many as 25 active gates.
E-mail This Article | Printer-Friendly Page |
Related News
- Intel Custom Foundry Certifies Synopsys Design Platform for Intel's 22nm FinFET Low Power Process Technology
- Intel describes 22-nm SoC process, not chips
- Intel sees quad-patterned path to 10 nm chips
- Tabula Confirms Move to Intel's 22nm Process Featuring 3-D Tri-Gate Transistors
- Rumor mill: Intel to roll 22-nm
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models