Princeton finds bugs in RISC-V architecture

April 19, 2017 // By Peter Clarke, EENews Europe

Researchers at Princeton University have discovered a series of memory-consistency errors in high-performance implementations of the RISC-V processor instruction specification.

If uncorrected these errors could cause hard-to-debug errors, crashes and security vulnerabilities in software on RISC-V chips, the research team said, but added that changes are being made to the specification ahead of a "formal release" of the ISA later in 2017.

RISC-V is an open-source instruction set architecture originally developed for research and education but which is now becoming a standard open architecture for industry implementations with backing from numerous companies including AMD, Google, Hewlett Packard, Huawei, IBM, Micron, Microsemi, Microsoft, Nvidia, NXP, Rambus, Qualcomm, Samsung and Western Digital. The technology, if widely adopted, could be disruptive to the business models of established IP licensors such as ARM and Imagination.

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