English
Process Detector (For DVFS and monitoring process variation)
Princeton finds bugs in RISC-V architecture
April 19, 2017 // By Peter Clarke, EENews Europe
Researchers at Princeton University have discovered a series of memory-consistency errors in high-performance implementations of the RISC-V processor instruction specification.
If uncorrected these errors could cause hard-to-debug errors, crashes and security vulnerabilities in software on RISC-V chips, the research team said, but added that changes are being made to the specification ahead of a "formal release" of the ISA later in 2017.
RISC-V is an open-source instruction set architecture originally developed for research and education but which is now becoming a standard open architecture for industry implementations with backing from numerous companies including AMD, Google, Hewlett Packard, Huawei, IBM, Micron, Microsemi, Microsoft, Nvidia, NXP, Rambus, Qualcomm, Samsung and Western Digital. The technology, if widely adopted, could be disruptive to the business models of established IP licensors such as ARM and Imagination.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related News
- Arm vs. RISC-V in 2025: Which Architecture Will Lead the Way?
- SensiML Expands Platform Support to Include the RISC-V Architecture
- New Automotive Grade Linux Platform Release Adds Cloud-Native Functionality, RISC-V Architecture and Flutter-Based Applications
- Radiation-Tolerant PolarFire® SoC FPGAs Offer Low Power, Zero Configuration Upsets, RISC-V Architecture for Space Applications
- RED Semiconductor announces VISC™ licensable high performance processor architecture for RISC-V
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset