Fraunhofer IIS Joins GLOBALFOUNDRIES FDXcelerator Program to Enable Dynamic Biasing IPs

Erlangen, Germany - April 25, 2017 -- The Fraunhofer Institute for Integrated Circuits IIS, a leading applied research and development center for ASIC, system-on-chip (SoC), and IP, today announced that it will offer dynamic biasing IPs for advanced SoC designs in GLOBALFOUNDRIES’ 22FDX® technology. This new capability offers dynamic adaption of block level performance versus power consumption ratio to customize and optimize SoC and ASIC designs.

On block level dynamic biasing and frequency scaling (DBFS), a technique similar to dynamic voltage and frequency scaling (DVFS) used in bulk CMOS technologies, can be used where a constant supply voltage is applied with dynamically changeable bias voltages to modify the FD-SOI transistors threshold voltages and therefore their speed and power consumption as needed. By that, regular and high Vt standard cells and memories can reduce power for slow operation or sleep and deep sleep modes in IoT or battery operated systems. Likewise, low and super low Vt cells and memories can be accelerated on demand for urgent data processing tasks or in high performance computing applications. This technology will allow more flexibility in high level design and will enable products to be easily customized to meet various and challenging market requirements.

“We are thrilled to have Fraunhofer join the rapidly-growing number of industry leaders in GF’s FDXcelerator Program,” said Alain Mutricy, senior vice president of Product Management at GF. “Fraunhofer's detailed knowledge of body bias low power design and ties to the European FD-SOI ecosystem will help accelerate adoption of 22FDX in key markets such as wearables and IoT.”

Dr. Norbert Weber, Head of Integrated Circuits and Systems at Fraunhofer IIS, adds: “With these dynamic biasing IPs, combined with the very low power and energy needs of GF's 22FDX® FD-SOI technology, IoT and mobile devices can be pushed to a new level.”

The FDXcelerator Partner Program builds upon GF’s industry-first FD-SOI roadmap, a lower-cost migration path for designers on advanced nodes that is optimized for lowpower applications. By participating, FDXcelerator Partners commit to provide specific resources, including EDA tools, IP, silicon platforms, reference designs, design services and packaging and test solutions. The program is based on an open framework which enables members to minimize development time and cost while simultaneously leveraging the inherent power and performance advantages of FDX technology.

Fraunhofer joins current FDXcelerator Program partners including Advanced Semiconductor Engineering, Inc. (ASE Group), Amkor Technology, ATTOPSEMI, Cadence, CEA Leti, Dreamchip, Encore Semi, Infosys, INVECAS, Mentor Graphics, QuickLogic, Rambus, Sasken, Synopsys, Sonics, and VeriSilicon.

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