Spectral announces "Enablement Package" for Silicon proven Reference SRAM designs on advanced process nodes
Memory Compilers, Embedded Memory Library developers, SRAM, MemoryIP, Design For Test & Repair
SOMERVILLE, NJ-- June 20, 2017 - Spectral Design & Test Inc. (SDT) today announced a complete reference flow on advanced process nodes that enables customers to quickly create industrial strength SRAM Memory Compilers. A combination of Spectral's proprietary Memory Development Platform (MDP) with a state of the art high-density low power architecture, customers can quickly create behavioral models, testbenches, schematics, layouts, timing, power & test views. Significant amount of time is spent in developing and maintaining software & hardware infrastructure necessary to create Memory Compilers. A reference design proven in silicon encapsulated in MDP gives designers a jump-start to create Memory Compilers without writing complex array tiling, analysis and characterization software. Spectral's reference designs can be seamlessly targeted on bulk-CMOS, FinFet & FDSOI processes. Spectral's MDP software is enabling customers to develop differentiated memory design and Memory Compiler creation at advanced technology nodes. Spectral software tools like MemoryCanvas™, MemoryTime™, MemComp™ have hooks to standard EDA tools ensuring that the customer's existing infrastructure is fully leveraged.
"Extreme requirements for high capacity low power SRAMs coupled with complicated design rules in the advanced nodes has significantly extended the cycle time, it is imminent that productivity gains are required for time-to-market and contain labor costs," said Deepak Mehta President & CEO of SDT. "We offer SOC library developers the best in class tools to create Memory Compilers that can be used to create design blocks internally and can be distributed license free to their end customers." Additionally, Spectral software comes with features that facilitate library developers to encrypt, license IP and distribute the Memory Compilers encapsulated in a very easy to use GUI. Spectral will demonstrate the development and delivery of Memory Compilers at the Design Automation Conference (DAC) 2017 by showcasing their products on the 16 & 40nm process nodes.
Affiliations
Spectral tools are developed & fully verified on an OpenAccess database (Si2 organization). SDT is a member of Cadence, Mentor Graphics & Synopsys partnership and eco systems.
Related News
- Spectral releases Silicon proven High Speed Low Power SRAM compilers in the 40/45nm CMOS/RFSOI process nodes targeted for a wide range of IOT & 5G Applications
- Spectral Releases Advanced Quality Assurance & Data Analytics tool to validate advanced node Memory Compilers
- MoSys' 1T-SRAM-R Memory is Silicon-Proven On UMC's 0.13 Micron Logic Process
- Spectral Design & Test Announces AI/ML Based Breakthrough Technology to Do Fast and Accurate Characterization & Validate Memory Compilers
- Intrinsic ID Optimizes SRAM PUF Security Technology for Advanced Process Nodes with QuiddiKey 4.x
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |