Synopsys and GLOBALFOUNDRIES Collaborate to Deliver Design Platform and IP Enablement for 7-nm FinFET Process
Enablement Includes Industry-Leading IC Compiler II P&R Solution and DesignWare Embedded Memory IP
MOUNTAIN VIEW, Calif., June 20, 2017 -- Synopsys, Inc. (Nasdaq: SNPS) today announced the enablement of the Synopsys Design Platform and DesignWare® Embedded Memory IP on GLOBALFOUNDRIES 7-nm Leading-Performance (7LP) FinFET process technology. Synopsys and GF collaboration on the new process addressed several new challenges specific to the 7LP process. This process is expected to deliver 40 percent more processing power and twice the area scaling compared to GF's 14nm FinFET process. Designers of premium mobile processors, cloud servers and networking infrastructure can take advantage of these benefits by confidently deploying the silicon-proven Synopsys Design Platform and Embedded Memory IP.
"GF's leading-performance 7-nm platform is exceeding initial performance targets and is now ready for customer designs," said Alain Mutricy, senior vice president of product management at GF. "GF and Synopsys have collaborated to provide designers with tools and methodology that fully leverage the power and highest absolute performance of our 7LP technology, and will allow customers to create innovative products across a range of high-performance applications."
GF and Synopsys worked together to ensure support of the comprehensive suite of Synopsys Design Platform digital implementation solutions for GF 7LP, including Design Compiler® Graphical synthesis, IC Compiler™ II place-and-route, IC Validator physical verification, PrimeTime® static timing analysis and StarRC™ extraction. To enable designers to achieve the full benefit of the GF 7LP process, the Synopsys tools employ advanced techniques including color track generation, pin color alignment checking and legalization, mixing of single-height and double-height physical boundary cells, power grid alignment to track and color-track aware routing.
The two companies are also collaborating on the development of Synopsys DesignWare Memory Compilers to deliver leading performance, power, area and yield for GF's 7-nm process technology. This joint effort consists of optimizing the GF 7LP process design rules and line patterns to achieve the best results. Early versions of the memory compilers will be on the GF 7LP process qualification vehicle.
"Synopsys and GF have always worked closely to address our customers' needs, including collaborations on FDSOI and 14-nm FinFET processes," said Michael Jackson, corporate vice president of marketing and business development in the Design Group at Synopsys. "With today's announcement, we are ready to enable designs on the 7LP process. We will continue to collaborate and ensure that our customers can get superior quality of results and faster time to results by using the Synopsys Design Platform and DesignWare Embedded Memory IP."
Availability
Support for Synopsys Design Platform is available today for GF process technologies. The DesignWare Embedded Memory and Interface IP for the GF 7LP process are in development. For more information on the collaboration between GF and Synopsys, please visit www.globalfoundries.com
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
|
Synopsys, Inc. Hot Verification IP
Related News
- Synopsys and TSMC Collaborate on Development of Interface and Foundation IP for 7-nm FinFET Process
- Synopsys and GLOBALFOUNDRIES Collaborate to Develop Broad Portfolio of DesignWare IP for 12LP FinFET Process
- TSMC Certifies Synopsys Design Platform for High-performance 7-nm FinFET Plus Technology
- Synopsys Successfully Tapes Out Broad IP Portfolio for TSMC 7-nm FinFET Process
- Synopsys Delivers Industry's First Multi-Protocol 25G PHY IP in 7-nm FinFET Process
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |