Process development partners eye IP sharing

The three semiconductor companies and foundry Taiwan Semiconductor Manufacturing Co. are working to make their process technologies compatible at the 90-nm node. Claasen said the partners met to consider how their R&D efforts could be made more efficient by dividing research tasks. Also, the partners will endeavor to avoid duplication by encouraging cooperation among IMEC; France's Laboratory for Electronics, Technology and Instrumentation (LETI); and International Sematech.

"In the past we all had a lot of efforts," Claasen said in an interview here during a Philips technology meeting for 300 of its top engineering managers. "ST worked with LETI, Philips with IMEC. Motorola's Dan Noble Center in Austin, Texas, was close to Sematech. We [the four Crolles partners] are all members of Sematech now, but all of this was not coordinated and it resulted in a waste of time."

Saving on equipment

The heightened cooperation will "definitely have an impact" on the 65-nm node, and even more so on the 45-nm technology node "now only in the early concept stages," Claasen said.

With Philips Semiconductors operating in the red, Claasen noted that if cooperation can save the purchase of unnecessary equipment, it relieves some of the pressure to reduce the ranks of s killed manpower. One 157-nm scanner costs tens of millions of dollars, he noted.

While parceling out research on materials and next-generation equipment brings its own set of conflicting agendas, Claasen said the sharing of intellectual property (IP) raises fundamental competitive issues. Like process technology, some forms of IP are a differentiator only if you are late to the party, Claasen said. An MPEG decoder either works or it doesn't, and "the only differentiation is if you don't have one."

In wireless communications, for example, the partners compete in the marketplace and are unlikely to share RF-related IP, Claasen said. To be sure, the four are working to develop a common set of libraries, circuit building blocks, memory compilers and other primitives needed to develop higher-level forms of IP.

But as for common design-for-reuse methodologies, IP repositories and EDA methodologies, Claasen said those topics are being discussed. His associates at the Phoenix meeting said a ll signs suggest that things are moving in that general direction.

Each of the four partners, for example, is developing "wrappers," which serve as a means of using large IP blocks to build up system-on-chip designs. While the Virtual Socket Interface Alliance (VSIA) also has worked to develop a standard form of wrapper, Claasen said the VSIA effort may be "too democratic" to meet the specific needs of the four Crolles partners. Instead, the companies are discussing whether it is in their interests to have a standard set of wrappers.

Rene Penning de Vries, the deputy chief technology officer at Philips Semiconductors, said that as the process technologies of the four partners become more fully compatible at the 90-nm node and beyond, the ability to exchange higher-level IP cores also becomes possible.