English
Atomic Rules launches TimeServo System Timer IP Core for FPGA
Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component
AUBURN, NH –September 1, 2017 -- Atomic Rules, a reconfigurable computing IP firm, is pleased to announce the launch of TimeServo, a Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component.
Atomic Rules TimeServo is a RTL IP core that serves the function of an FPGA’s System Timer or Clock. Although specifically designed to support the needs of line-rate independent packet timestamping, TimeServo may find use
where there is the need for a high-resolution, modest-accuracy timebase. TimeServo’s PI-DPLL allows a local TCXO to be disciplined by an external 1 PPS signal to achieve excellent syntonicity.
In conjunction with timestamp-capable MACs (not included) and host-control software (as-is examples provided),
TimeServo is a vital and central component of an IEEE-1588/PTP system.
AtomicRules TimeServo
TimeServo IP Core Pricing and Availability
The Atomic Rules TimeServo IP core for FPGA is available for purchase. TimeServo includes “As is” software control utility to set/get common settings as well as observe behavior and example design using Atomic Rules Arkville (Arkville NOT Included) showing application with IEEE-1588 Precision Time Protocol (PTP). Contact us for pricing information.
About Atomic Rules
Atomic Rules is an electrical engineering consultancy providing its clients with effective solutions to problems involving interconnection networks and reconfigurable computing. Their practice employs scalable, rule-based methods to tackle complex concurrency among heterogeneous processors. Atomic Rules understands the limitations of composing complex processor interactions using conventional RTL methods. To address this challenge, they use tools and techniques inspired by functional programming. Beyond RTLs, they specialize in creating source codes written in Bluespec SystemVerilog, a vehicle for code correctness, portability and reuse. Atomic Rules provides its clients with expert SoC/FPGA competencies that build upon RTL/ESL design and verification techniques – not reinvent them. For more information, visit www.atomicrules.com.
|
||||||
Related News
- Atomic Rules announces DPDK-aware FPGA/GPP data mover
- Algo-Logic Systems Launches Third Generation FPGA Accelerated CME Tick-To-Trade System
- Algo-Logic Systems Launches FPGA Accelerated CME Tick-To-Trade System
- ProDesign launches Virtex 7 2000T multi FPGA based Prototyping System
- Xilinx Launches First Design Platforms for Accelerating 7 Series FPGA Design Productivity and System Integration
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |