Hot Chips Spotlights Chip Stacks
Chiplets seen as the future of IP blocks
Rick Merritt, EETimes
8/23/2017 00:01 AM EDT
CUPERTINO, Calif. – A U.S. research effort aims to nurture an ecosystem for designing semiconductors from plug-and-play chiplets. It arrives at a time when rivals such as Intel and Xilinx are using proprietary packaging techniques to differentiate competing FPGAs.
Over the next eight months, the Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program under the Defense Advanced Research Projects Agency aims to define and test open chip interfaces. Within three years it hopes multiple companies will use the links to connect a wide range of die to form sophisticated components.
Intel has signed up for the program, and others are expected to follow soon. Internally, the x86 giant is debating whether to open up parts of its embedded multi-die interconnect bridge (EMIB) as part of its participation. The company gave the most detailed look at EMIB to date at the Hot Chips event here.
E-mail This Article | Printer-Friendly Page |
Related News
- eSilicon to debut AI Accelerator software and a new chiplet model at Hot Chips 2019
- THINCI Inc. Will Present Its Next-Generation Graph Streaming Processor Architecture At the Hot Chips Symposium
- Achronix to Attend HOT CHIPS: A Symposium on High Performance Chips
- IPFlex to Introduce Industry-Leading Dynamically Reconfigurable Processor and C-Based Design Environment at Hot Chips 17 and HPEC 2005
- sureCore teams with Sarcina to package cryo chips
Breaking News
- Micon Global and Silvaco Announce New Partnership
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition