Rambus Delivers High-Speed SerDes Interface Solutions on GLOBALFOUNDRIES FX-14 ASIC Platform for Data Center and Enterprise
Suite of silicon-proven PHYs on 14nm LPP process technology maximize performance and flexibility
SUNNYVALE, Calif. – Oct. 12, 2017 – Rambus Inc. (NASDAQ: RMBS), a leading provider of semiconductor and IP products, today announced the availability of a suite of silicon-proven, high-speed SerDes solutions including 16G MPSL (multi-protocol serial link), 30G C2C (chip-to-chip) and 30G VSR (very short reach) PHYs developed for GLOBALFOUNDRIES high-performance FX-14™ ASIC platform. Built on the GLOBALFOUNDRIES’ 14nm FinFET (14LPP) process technology, the Rambus SerDes PHYs are optimized for power and area at peak bandwidth, generating Ethernet speeds up to 100Gb and beyond for high-speed wireline, wireless, 5G network infrastructure, high-performance servers, storage, connectivity and compute applications.
“Data traffic and bandwidth demands have exploded, driving the insatiable need for highly optimized, high-performance semiconductor solutions,” said Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division. “Through our collaboration with GLOBALFOUNDRIES, Rambus is delivering robust high-speed interface IP that enables innovative chips and systems designed specifically for the Data Center and Communications markets and helping GLOBALFOUNDRIES deliver value to its customers through tested solutions.”
“Next-generation systems for cloud and communications must deliver more performance and handle more complexity than ever before,” said Kevin O’Buckley, vice president of product development at GLOBALFOUNDRIES. “Working together with Rambus enables us to provide ASIC solutions to our customers with a range of high-speed SerDes interfaces that have been optimized for power and area at peak bandwidth while maintaining complete compatibility with industry standards.”
The Rambus SerDes PHYs include a Physical Media Attachment (PMA) hard macro and Physical Coding Sub-layer with Built-in Self-Test (PCS-BIST) soft macro. The PHYs can also be configured to multiple channel widths and packaging options, which simplifies integration and maximizes design flexibility.
For additional information on Rambus SerDes Interface Solutions, please visit rambus.com/serdes.
|
Related News
- Rambus Introduces High Bandwidth Memory PHY on GLOBALFOUNDRIES FX-14 ASIC Platform using 14nm LPP Process Technology
- EXTOLL collaborates with BeammWave and GlobalFoundries as a Key SerDes IP Partner for Lowest Power High-Speed ASIC
- Rambus Delivers PCIe 6.0 Interface Subsystem for High-Performance Data Center and AI SoCs
- Rambus and GLOBALFOUNDRIES to Deliver High-Speed SerDes on 22FDX for Communications and 5G Applications
- GLOBALFOUNDRIES Announces Industry's First 300mm SiGe Foundry Technology to Meet Growing Data Center and High-Speed Wireless Demands
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |