Codasip Announces Bk5-64, a New 64-bit RISC-V Processor
Brno, Czech Republic – November 28th, 2017 – Codasip, the leading supplier of RISC-V® embedded processor IP, today announced that it has expanded its Berkelium processor portfolio to include the Bk5-64, its first implementation of the 64-bit RISC-V ISA.
Codasip now offers customers the broadest selection of RISC-V processors in the market, spanning from the ultra-low-power zero-stage Bk1 to the high-data-bandwidth, energy-efficient Bk5-64. All Berkelium processors are generated via the unique Codasip Studio customization tool, allowing for fast configuration and optimization of the cores.
“With the rapid expansion of data-intensive applications such as storage and wireless networking, the market is asking for embedded processor solutions with the right balance of performance and energy efficiency that 64-bit computing requires,” stated Karel Masařík, founder and CEO of Codasip. “By introducing the Bk5-64, Codasip is addressing the need for affordable 64-bit embedded processors, complete with a state-of-the-art LLVM-based software development toolchain with advanced profiling.”
RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
Said Rick O’Connor, Executive Director of the non-profit RISC-V Foundation, “Today’s announcement from Codasip shows continued growth of the RISC-V architecture and the industry’s need for a new open, free ISA. We look forward to seeing more developments from Codasip and others from the RISC-V ecosystem in the future.”
The Berkelium Bk5-64 RISC-V processor is available later in Q4 of 2017.
About Codasip
Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.
Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.
For more information about Codasip’s products and services, visit www.codasip.com.
|
Codasip Hot IP
Related News
- Codasip introduces best-in-class RISC-V core for power-efficient applications
- Codasip announces next-generation RISC-V processor family for Custom Compute
- Semidynamics announces largest, fully customisable Vector Unit in the RISC-V market, delivering up to 2048b of computation per cycle for unprecedented data handling
- Blueshift Memory to use Codasip custom compute to develop new memory-efficient processor technology
- SEGGER adds 64-bit RISC-V support to Embedded Studio
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |