Averant's Solidify 6.5 Significantly Improves Combinational and Sequential Equivalency Checking and Clock Domain Crossing Checks
Oakland, Calif. – December 12, 2017 – Averant Inc., the First In Formal™ leader in property verification of RTL designs for digital circuits, today announced the release of Solidify 6.5. Some of the highlights of this release are listed below.
- Machine learning inspired signal matching in SEC/CEC. The first step in equivalency checking is identifying candidate signals which are equal. Release 6.5 extends capabilities of prior releases with many new ideas including some inspired by statistical learning and machine learning technologies.
- Speed improvements, complete difficult problems, and better library support in CEC. Release 6.5 provides improved library support and several new techniques to improve speed and complete difficult problems.
- New usability features in clock crossing inspired by relational databases. Using ideas from relational databases, release 6.5 offers the users a variety of ways to view and analyze their clock domain crossing signals in the same way that the SQL database language allows for browsing and analyzing data.
Release 6.5 also contains improvement in property verification, coverage, debugging, GUI, PSL and SVA support.
"Release 6.5 was the result of close collaboration with our customers and made immediate impact on their verification challenges" commented Ramin Hojati, president of Averant. "This all happened while ideas from the rest of computer science were implemented in Solidify, enriching our development team and customers' experiences".
Availability
Release 6.5 is available for use immediately.
About Averant
Averant Inc. is a privately held EDA firm specializing in formal verification of digital designs. Averant’s signature product is Solidify, a robust platform for property, protocol, and automatic design checks – all without the need for simulators or test vectors. Averant's tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, visit http://www.averant.com.
|
Related News
- Aldec sets a new paradigm with a single platform for Design Rule Checking and Clock Domain Crossing Verification for FPGA and ASIC designs
- Silicon Library Adopts Averant's Solidify Automated Checks Using CDC Inc. EDA Cloud Services
- Mentor Graphics expands formal verification's reach with new cross-platform GUI and apps for sequential logic equivalence checking and CDC gate-level analysis
- Aldec launches ALINT-PRO-CDC delivering comprehensive CDC Verification Strategies for SoC and FPGA Designs
- Averant Adds RTL and Gate Level Combinational Equivalency Checker
Breaking News
- intoPIX Powers Ikegami's New IPX-100 with JPEG XS for Seamless & Low-Latency IP Production
- Tower Semiconductor and Alcyon Photonics Announce Collaboration to Accelerate Integrated Photonics Innovation
- Qualcomm initiates global anti-trust complaint about Arm
- EnSilica Agrees $18m 7 Year Design and Supply ASIC Contract
- SiliconIntervention Announces Availability of Silicon Based Fractal-D Audio Amplifier Evaluation Board
Most Popular
- Qualcomm initiates global anti-trust complaint about Arm
- Siemens acquires Altair to create most complete AI-powered portfolio of industrial software
- Alphawave Semi Reveals Suite of Optoelectronics Silicon Products addressing Hyperscaler Datacenter and AI Interconnect Market
- EnSilica Agrees $18m 7 Year Design and Supply ASIC Contract
- Rapidus Announces Strategic Partnership with Quest Global to Enable Advanced 2nm Solutions for the AI Chip Era
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |