SoC-e Announces New Release of Managed Ethernet Switch (MES) IP Core Supporting DLR for Ethernet/IP
January 24, 2018 -- Device Level Ring (DLR) is a Layer-2 protocol that provides media redundancy in a ring topology. The DLR protocol is intended primarily for implementation in Ethernet/IP end-devices that have two Ethernet ports and embedded switch technology. The DLR protocol provides fast network fault detection and reconfiguration in order to support the most demanding control applications.
A DLR network includes at least one node configured to be a Ring Supervisor, and any number of Beacon Based Nodes. It is assumed that all the ring nodes have at least two Ethernet ports and incorporate embedded switch technology.
The new realease of SoC-e’s MES IP Core (Managed Ethernet Switch) fully supports DLR protocol. The IP Core allows to implement a DLR end-device, with embedded switching capabilities and supports multiple Ethernet interfaces. The following network node configurations can be implemented with the MES IP Core:
- Ring Supervisor Node
- Beacon Based Node
|
Related News
- SoC-e's Managed Ethernet Switch now supports up-to 32 ports
- The new release of SoC-e IEEE 1588 IP Core supports 10 Gigabit Ethernet
- SoC-e Announces 10G Multiport TSN Switch Release
- Stage Tec introduces HSR for Professional Audio Broadcasting using SoC-e Technology
- SoC-e's MTSN Switch IP Core solution now supports 802.1AB (LLDP)
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |